参数资料
| 型号： | ADP1046ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 52/92页 |
| 文件大小： | 0K |
| 描述： | IC DGTL CTRLR 32LFCSP |
| 标准包装： | 5,000 |
| 应用： | 电源 |
| 输入电压： | 0 V ~ 1.6 V |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 20mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 带卷 (TR) |
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ADP1046
Data Sheet
Register 0x0F allows the user to program the ADP1046 to ignore the specified flags until the end of the soft start ramp time. The UVP
and ACSNS flags are always active during soft start.
Table 15. Register 0x0F—Soft Start Blank Fault Flags Register
Bits
7
Bit Name
Blank SR
R/W
R/W
Description
Setting this bit means that the SR1 and SR2 PWM outputs are not enabled until the end of the soft
start ramp time.
6
5
4
Blank OTP
Blank FLAGIN
Blank local OVP
R/W
R/W
R/W
Setting this bit means that the OTP flag is ignored until the end of the soft start ramp time.
Setting this bit means that the FLAGIN flag is ignored until the end of the soft start ramp time.
Setting this bit means that the local OVP flag is ignored until the end of the soft start ramp time.
(accurate and fast)
3
2
1
0
Blank load OVP
Blank CS2 accurate
OCP
Blank CS1 accurate
OCP
Blank CS1 fast OCP
R/W
R/W
R/W
R/W
Setting this bit means that the load OVP flag is ignored until the end of the soft start ramp time.
Setting this bit means that the CS2 accurate OCP flag is ignored until the end of the soft start
ramp time.
Setting this bit means that the CS1 accurate OCP flag is ignored until the end of the soft start
ramp time.
Setting this bit means that the CS1 fast OCP flag is ignored until the end of the soft start ramp time.
VALUE REGISTERS
Table 16. Register 0x10—First Flag ID
Bits
[7:4]
[3:0]
Bit Name
Reserved
First flag ID
R/W
R
R
Description
Reserved.
These bits record the flag that was set first. Restarting the power supply resets this register. Reading
this register also resets the register.
Bit 3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Fault Register
None
Register 0x01, Bit 3
Register 0x01, Bit 2
Register 0x03, Bit 1
Register 0x00, Bit 2
Register 0x00, Bit 1
Register 0x00, Bit 0
Register 0x01, Bit 1
Register 0x01, Bit 0
Register 0x02, Bit 0
Register 0x02, Bit 7
Register 0x01, Bit 6
Register 0x01, Bit 5
Register 0x01, Bit 7
Register 0x02, Bit 5
Register 0x03, Bit 2
Flag
No flag
VCORE OV
VDD OV
EEPROM CRC fault
CS1 fast OCP
CS1 accurate OCP
CS2 accurate OCP
Load OVP
Local OVP (fast and accurate)
FLAGIN
OTP
UVP
CS2 reverse voltage
Voltage continuity
Share bus
ACSNS
Table 17. Register 0x11—RTD Current Source
Bits
[7:6]
[5:0]
Bit Name
RTD current setting
Current trim
R/W
R/W
R/W
Description
These bits set the size of the current source on the RTD pin.
Bit 7
Bit 6
Current Source (μA)
0
0
10
0
1
20
1
0
30
1
1
40
These six bits are used to trim the current source on the RTD pin. Each LSB corresponds to 160 nA,
independent of the RTD current setting selected in Register 0x11[7:6].
Rev. B | Page 52 of 92
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