- 您现在的位置：买卖IC网 > PDF目录16077 > IPR-SDRAM/DDR2 (Altera)IP DDR2 SDRAM CONTROLLER RENEW PDF资料下载
参数资料
| 型号： | IPR-SDRAM/DDR2 |
| 厂商： | Altera |
| 文件页数： | 102/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR2 SDRAM CONTROLLER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR2 SDRAM 控制器 |
| 许可证： | 续用许可证 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页当前第102页第103页第104页第105页第106页
D–2
Adjust the PLL Phases
Adjust the PLL Phases
There is no automatic setup of the fedback PLL, or the resyncronization and
postamble clock phases in fedback clock DQS mode (refer to Figure A–2 on page A–6 ).
To adjust the PLL phases, follow these steps:
1. On the Manual Timing tab, turn on Manual resynchronization control and
Manual postamble control .
2. In Postamble clock setting , choose Dedicated clock .
3. Click Show Timing Estimates .
1
The following parameters must be set in the given order.
4. Balance the following setup and hold time properties on the Show Timing
Estimates window, by adjusting the relevant parameter on the Manual Timing
tab.
a. For Stage 1 Resynchronization , adjust the resynchronization fedback clock
phase.
b. For Stage 2 Resynchronization , adjust the resynchronize captured read data in
cycle.
c. For Stage 1 Postamble Control , adjust the postamble dedicated clock phase.
d. For Stage 1 Postamble Control , adjust the postamble cycle.
You can now set up constraints and generate your custom variation.
Assign Pins
When you compile a project, the add_constraints_for_ < variation name > .tcl script
automatically assigns the DQ/DQS pins. To assign the other pins that are needed for
the DDR2 SDRAM interface on the Stratix II Memory Board 2, run the
< install directory > /lib/stratix_s2mb2_pins.tcl .
Place the Fedback PLL
The fedback PLL needs to be driven directly from the input pin, and not routed
through the FPGA, otherwise the Quartus II software issues a warning and your
design does not meet timing.
On the Stratix II Memory Board 2 the fedback clock input pin is on the side of the
device, and the memory interface is on the top. Because the example design feeds the
DLL from the fedback PLL by default, the PLL is automatically placed on the top and
its clock input is therefore routed through the FPGA. To improve the design’s
timing, you should manually place the PLL on the side and drive the DLL input from
the system clock. If the fedback clock input pin is on the same side as the DQ pins, the
DLL may be fed from the fedback PLL.
? March 2009 Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| GEM31DTBN-S189 | CONN EDGECARD 62POS R/A .156 SLD |
| GEM31DTBH-S189 | CONN EDGECARD 62POS R/A .156 SLD |
| GEM31DTBD-S189 | CONN EDGECARD 62POS R/A .156 SLD |
| GEM31DTAN-S189 | CONN EDGECARD 62POS R/A .156 SLD |
| 10YXJ2200M10X20 | CAP ALUM 2200UF 10V 20% RADIAL |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IP-RSENC | 功能描述:开发软件 Reed-Solomon Encoder MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SLITE2 | 功能描述:开发软件 SerialLite II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
发布紧急采购，3分钟左右您将得到回复。