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参数资料
| 型号： | IPR-SDRAM/DDR2 |
| 厂商： | Altera |
| 文件页数： | 54/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR2 SDRAM CONTROLLER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR2 SDRAM 控制器 |
| 许可证： | 续用许可证 |
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3–18
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f
Chapter 3: Functional Description
Device-Level Description
The testbench instantiates a DDR or DDR2 SDRAM DIMM model, a reference clock
for the PLL, and model for the system board memory trace delays. When
test_complete is detected high, a test finished message is printed out, which
shows whether the test has passed.
Altera does not provide a memory simulation model. You must obtain one from your
memory vendor.
Constraints
IP Toolbench generates a constraints script, add_constraints_for_ <variation name> .tcl ,
which is a set of Quartus II assignments that are required to successfully compile the
example design.
1
When the constraints script runs, it creates another script,
remove_constraints_for_ <variation name> .tcl , which you may use to remove the
constraints from your design.
The constraints script implements the following types of assignments:
■
■
■
■
■
■
■
■
■
Capacitance loading for SDRAM interface pins
I/O standard to SSTL-2 class II for DDR SDRAM interface pins (SSTL-18 class II
for DDR2 SDRAM)
Current strength set to “min” for Stratix devices
DM, DQ, and DQS pin placement (except for non-DQS mode on Stratix devices)
Resynchronization and postamble registers placement
I/O register placement for Cyclone series
Synthesis “Don’t Optimize” set for the datapath logic
Address and control fast output register constraints
DQS frequency and delay settings for Cyclone devices
1
As the static timing analysis performed after the design compiles requires that the all
the clocks in the datapath are global, you must ensure you do not use regional clocks
for the datapath logic.
Table 3–6. Methods for Logic Placement Constraints
Device Family
Stratix II/Stratix II GX
Stratix/Stratix GX
Cyclone II
Cyclone
Capture Registers
—
—
LAB placement
LE placement
Resynchronization Registers
LAB placement
LogicLock region constraints
LAB placement
LE placement
? March 2009 Altera Corporation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IP-RSENC | 功能描述:开发软件 Reed-Solomon Encoder MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SLITE2 | 功能描述:开发软件 SerialLite II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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