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| 型号： | IPR-SDRAM/DDR2 |
| 厂商： | Altera |
| 文件页数： | 103/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR2 SDRAM CONTROLLER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR2 SDRAM 控制器 |
| 许可证： | 续用许可证 |
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D–3
Update the PLL Phases
Update the PLL Phases
After compilation you should return to IP Toolbench and update the PLL phases. The
verify timing script reports the margins on the various registers in the read path. To
update the PLL phases, follow these steps:
1. Edit your custom variation in IP Toolbench.
2. On the Manual Timings tab, turn on Use the results of the last comile to estimate
setup and hold margins .
IP Toolbench uses initial estimates based on a nominal design. After you run the
verify timing script for the first time, IP Toolbench uses data from your design to
make more accurate estimates of the margins.
3. Adjust the PLL phases to meet timing.
4. Recompile the design. The verify timing script should report improved margins.
5. To balance the setup and hold margins, or to fix negative margins return to step
1
1
The calculation of setup and hold margins for the registers driven from the
fedback PLL can appear confusing—a small adjustment of the phase can
cause a large change in setup and hold margins. The timing script
automatically calculates the cycle that the data is transferred in. A small
change to the phase can change the cycle on which the data is transferred,
which results in a large change on the setup and hold margins.
If the second resynchronization path does not meet timing, or to increase
the available margin, add a maximum-data-arrival-skew constraint
between the first and second stage resynchronization registers. This
constraint constrains the routing and placement of these registers and
reduces skew across this bus. Add these constraints by executing the
following commands in the Tcl Console:
set_instance_assignment -name TPD_REQUIREMENT "1.6 ns" –from
*resynched_data* -to *fedback_resynched_data*'
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE SPEED
? March 2009
Altera Corporation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IP-RSENC | 功能描述:开发软件 Reed-Solomon Encoder MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SLITE2 | 功能描述:开发软件 SerialLite II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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