- 您现在的位置：买卖IC网 > PDF目录16077 > IPR-SDRAM/DDR2 (Altera)IP DDR2 SDRAM CONTROLLER RENEW PDF资料下载
参数资料
| 型号： | IPR-SDRAM/DDR2 |
| 厂商： | Altera |
| 文件页数： | 99/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR2 SDRAM CONTROLLER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR2 SDRAM 控制器 |
| 许可证： | 续用许可证 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页当前第99页第100页第101页第102页第103页第104页第105页第106页
C. HardCopy II Design Walkthrough
This walkthrough explains the additional steps that are needed to use the DDR or
DDR2 SDRAM Controller MegaCore function in a HardCopy II design.
f
You can create a HardCopy II design either with the main target set to a HardCopy II
device and a Stratix II migration device, or with the main revision targeting a Stratix II
device and a companion revision targeting HardCopy II device.
To create a HardCopy II design, follow these steps:
1. Create a new Quartus II project and choose a family, a device, and a companion
device.
1
Altera recommends you choose a –4 speed grade device.
2. Launch IP Toolbench from the MegaWizard Plug-In Manager
3. Parameterize your custom variation.
4. Choose the constraints.
1
HardCopy II devices do not have dedicated hardware for DDR or DDR2
SDRAM capture on as many pins as the Stratix II companion, so there are
less DQS groups available.
5. Generate the variation.
6. Compile the design, which adds placement constraints for critical registers in the
read part of the datapath, and produces a report of the predicted timing margins.
7. The timing report that appears automatically is not available to the HardCopy
Design Centre, therefore add a set of timing constraints to help timing closure, by
running the DDR and DDR2 SDRAM timing wizard (DTW)—choose Tcl scripts
(Tools menu) and choose dtw .
f
8. To save time re-entering the parameters of the DDR or DDR2 SDRAM Controller
MegaCore function, import the parameters from the < variation
name > _ddr_setting.txt file, by clicking Import… on the third page of the wizard.
9. The DTW also needs an estimate of the t CO on the pins that drive the clock to the
DDR or DDR2 SDRAM. When the design has been compiled extract these
automatically in the relevant pane of the wizard.
10. Click Finish . The DTW adds timing constraints to the project, which are preserved
when migrating to HardCopy II devices.
? March 2009
Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| GEM31DTBN-S189 | CONN EDGECARD 62POS R/A .156 SLD |
| GEM31DTBH-S189 | CONN EDGECARD 62POS R/A .156 SLD |
| GEM31DTBD-S189 | CONN EDGECARD 62POS R/A .156 SLD |
| GEM31DTAN-S189 | CONN EDGECARD 62POS R/A .156 SLD |
| 10YXJ2200M10X20 | CAP ALUM 2200UF 10V 20% RADIAL |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IP-RSENC | 功能描述:开发软件 Reed-Solomon Encoder MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SLITE2 | 功能描述:开发软件 SerialLite II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
发布紧急采购，3分钟左右您将得到回复。