参数资料
型号: IPR-SDRAM/DDR2
厂商: Altera
文件页数: 73/106页
文件大小: 0K
描述: IP DDR2 SDRAM CONTROLLER RENEW
标准包装: 1
系列: *
类型: MegaCore
功能: DDR2 SDRAM 控制器
许可证: 续用许可证
Chapter 3: Functional Description
Parameters
Figure 3–21. Additional Pipeline Registers—A = On, B = Off, C= On
3–37
FSM
A
B
N egati v e Edge
Address and Command
O u tp u t
clk
Figure 3–22. Additional Pipeline Registers—A = On, B = On, C= On
FSM
A
B
N egati v e Edge
Address and Command
O u tp u t
clk
addrcmd_clk
Table 3–17 shows the DLL reference clock options.
Table 3–17. DLL Reference Clock Options
Parameter
Insert logic to allow the DLL
to update only during the
memory refresh period
Range
On or off
Description
For Stratix devices, Altera recommends you turn on this option to switch
off the DLL during read operations and so reduce jitter. For Stratix II
devices, Altera recommends you turn on this option only if your memory
interface spans two sides of the device or if you intend to share a DLL
between two or more interfaces on two sides of the device. Refer to “DLL
Controller Timings
The memory timing parameters on the controller timings tab adjust the controller ’s
timing to meet the timing parameters specified in the datasheet for the memory
devices. The Controller Timings tab shows the following three columns of
information:
Required
Cycles
Actual
The Required column specifies the timing requirements from the memory device
datasheet; these requirements can be minimum or maximum times. The values in the
required column are automatically set by your chosen memory device from the
Memory Device list.
The Cycles column specifies the number of cycles that the controller uses to meet
these timing requirements.
The Actual column reports the actual time that the controller uses, based on the
values in the cycles column and the clock speed.
? March 2009
Altera Corporation
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