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参数资料
| 型号： | IPR-SDRAM/DDR2 |
| 厂商： | Altera |
| 文件页数： | 25/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR2 SDRAM CONTROLLER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR2 SDRAM 控制器 |
| 许可证： | 续用许可证 |
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Chapter 2: Getting Started
2–15
MegaWizard Plug-In Manager Design Flow
Constraints
To choose the constraints for your device, follow these steps:
1. Click Step 2: Constraints in IP Toolbench.
2. Choose the positions on the device for each of the DDR SDRAM byte groups. To
place a byte group, select the byte group in the drop-down box at your chosen
position.
1
1
The floorplan matches the orientation of the Quartus II floorplanner. The
layout represents the die as viewed from above. A byte group consists of
four or eight DQ pins, a DM pin, and a DQS pin.
IP Toolbench chooses the correct positions, if you are using an Altera board
preset.
Set Up Simulation
An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model
produced by the Quartus II software. The model allows for fast functional simulation
of IP using industry-standard VHDL and Verilog HDL simulators.
c
You may only use these simulation model output files for simulation
purposes and expressly not for synthesis or any other purposes. Using these
models for synthesis will create a nonfunctional design.
To generate an IP functional simulation model for your MegaCore function, follow these steps:
1. Click Step 3: Set Up Simulation in IP Toolbench.
2. Turn on Generate Simulation Model .
3. Choose the language in the Language list.
1
To use the IP Toolbench-generated testbench, choose the same language
that you chose for your variation.
4. Some third-party synthesis tools can use a netlist that contains only the structure
of the MegaCore function, but not detailed logic, to optimize performance of the
design that contains the MegaCore function. If your synthesis tool supports this
feature, turn on Generate netlist .
5. Click OK .
Generate
To generate your MegaCore function, follow these steps:
1. Click Step 4: Generate in IP Toolbench.
directory. The names and types of files specified in the IP Toolbench report vary
based on whether you created your design with VHDL or Verilog HDL.
? March 2009
Altera Corporation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IP-RSENC | 功能描述:开发软件 Reed-Solomon Encoder MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SLITE2 | 功能描述:开发软件 SerialLite II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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