- 您现在的位置：买卖IC网 > PDF目录16077 > IPR-SDRAM/DDR2 (Altera)IP DDR2 SDRAM CONTROLLER RENEW PDF资料下载
参数资料
| 型号： | IPR-SDRAM/DDR2 |
| 厂商： | Altera |
| 文件页数： | 79/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR2 SDRAM CONTROLLER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR2 SDRAM 控制器 |
| 许可证： | 续用许可证 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页当前第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页
A. Manual Timing Settings
Parameters
For more information on the resynchronization options, refer to “Resynchronization”
Table A–1. Resynchronization Options (Part 1 of 2)
Parameter
Range
Description
Reclock resynchronized data
to the positive edge
Automatic, Always, or Never When this option is set to “Always” the wizard inserts a set
of positive edge system clock registers in the read data path
and delays the read data valid signal appropriately. The extra
registers are useful if you are resynchronizing with a phase
other than the positive edge of the system clock, but at the
expense of a clock cycle of latency. Choosing Never
produces lower latency. However, it is then your
responsibility to reclock the read data to the positive edge of
the system clock. When this option is set to Automatic , the
wizard decides whether or not to insert the extra set of
registers based on the choice of resynchronization edge and
system clock.
When the resynchronization clock phase is close to the
positive edge of the system clock, this option inserts an
additional set of registers, clocked on the negative edge of
system clock, between the resynchronization clock domain
and the system clock domain.
Manual resynchronization
control
Resynchronize captured read
data in cycle
Resynchronization clock
setting
On or off
0 to 6
0 ( clk , rising edge),
90 ( write_clk , falling
edge),
180 ( clk , falling edge)
270 ( write_clk , rising
edge), or
dedicated
Turn on to specify the details of the resynchronization clock.
Otherwise, the details are calculated automatically based on
system timing. You must turn on this option when you turn
on the DQS mode and the fedback PLL options.
The number of cycles of delay to allow for the round trip
delay.
Defines which clock to use for resynchronization: the system
clock, the write clock (a 90 ° advanced version of the system
clock), or a dedicated resynchronization clock. Also defines
which edge of the chosen clock to use to resynchronize the
captured data. If you select falling edge, the data path
automatically inserts inverters on the clock inputs to the
resynchronization registers.
When the resynchronization clock is set to either the system
clock or the write clock, you cannot alter the phase of the
resynchronization clock. To alter the resynchronization phase
clock, select the resynchronization clock as dedicated and
set the required phase.
? March 2009
Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| GEM31DTBN-S189 | CONN EDGECARD 62POS R/A .156 SLD |
| GEM31DTBH-S189 | CONN EDGECARD 62POS R/A .156 SLD |
| GEM31DTBD-S189 | CONN EDGECARD 62POS R/A .156 SLD |
| GEM31DTAN-S189 | CONN EDGECARD 62POS R/A .156 SLD |
| 10YXJ2200M10X20 | CAP ALUM 2200UF 10V 20% RADIAL |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IP-RSENC | 功能描述:开发软件 Reed-Solomon Encoder MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SLITE2 | 功能描述:开发软件 SerialLite II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
发布紧急采购，3分钟左右您将得到回复。