参数资料
型号: IPR-SDRAM/DDR2
厂商: Altera
文件页数: 56/106页
文件大小: 0K
描述: IP DDR2 SDRAM CONTROLLER RENEW
标准包装: 1
系列: *
类型: MegaCore
功能: DDR2 SDRAM 控制器
许可证: 续用许可证
3–20
1
Chapter 3: Functional Description
Interfaces & Signals
Writes
Figure 3–13 on page 3–20 shows three write requests of different sizes, the first two to
sequential addresses and the third to a new row and bank. The controller allows you
to use any burst length up to the maximum burst length set on the memory device.
For example, if you select burst length of 8 for your DDR SDRAM memory, the
controller allows bursts of length 1, 2, 3, and 4 (2, 4, 6, and 8 on the DDR SDRAM
side).
The concept is similar for DDR2 SDRAM although only burst lengths 1 and 2 (2 and 4
on the DDR2 SDRAM side) are available.
Figure 3–13. Writes
[3]
[1]
[2] [4]
[5]
[6]
clk
Local Interface
local_read_req
local_write_req
local_ready
local_size
1
2
4
local_cs_addr (1)
local_row_addr (1)
local_bank_addr (1)
1
010
1
3
210
3
0
000
0
local_col_addr (1)
local_wdata_req
local_wdata
020 021 030
9275FF45 1A27 C510A 8 4BD259
000
A04A
local_be
2
1
3
2
DDR SDRAM
Interface
ddr_cs_n
F
D
F
D
F
7
F
7
F
ddr_cke
F
ddr_a
000
010 000 040 042
0000
210 000 060
000
ddr_ba
0
1
0
1
0
3
0
3
0
DDR Command (2)
NOP
ACT NOP
WR
NOP
ACT NOP WR
NOP
ddr_ras_n
ddr_cas_n
ddr_we_n
ddr_dm(0)
ddr_dq
ddr_dqs(0)
Notes to Figure 3–13 :
(1) The local_cs_addr , l ocal_row_addr , local_bank_addr , and local_col_addr signals are a representation of the
local_addr signal.
(2) DDR Command shows the command that the command signals ( ddr_ras_n , ddr_cas_n and ddr_we_n ) are issuing.
? March 2009 Altera Corporation
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