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参数资料
| 型号： | IPR-SDRAM/DDR2 |
| 厂商： | Altera |
| 文件页数： | 80/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR2 SDRAM CONTROLLER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR2 SDRAM 控制器 |
| 许可证： | 续用许可证 |
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A–2
Parameters
Table A–1. Resynchronization Options (Part 2 of 2)
Parameter
Dedicated clock phase
Fed-back clock phase
Insert intermediate
resynchronization registers
0 to 359
0 to 359
On or off
Range
Description
This parameter is available only when you select Dedicated
for the Resynchronization clock setting. You can enter the
phase of the dedicated resynchronization clock for timing
analysis. IP Toolbench uses this value to set up the PLL
phase shift.
Allows you to enter the phase of the fed-back clock that is
used for timing analysis. IP Toolbench uses this value to set
up the PLL phase shift.
When turned on, an extra pipeline register, clocked on the
negative edge of system clock, is inserted in the read path
after the resynchronization registers. Turn on when the
resynchronization clock is too close to the system clock for
reliable transfer between them. Refer to “Intermediate
f
Table A–2. Postamble Options (Part 1 of 2)
Parameter
Manual postamble control
Enable DQS postamble logic
Insert intermediate
postamble registers
Postamble cycle
On or off
On or off
On or off
0 to 6
Range
Description
Turn on to specify the details of the postamble logic clock
and to set the postamble clock phase manually. Otherwise,
the details are calculated automatically based on system
timing.
This option is only available when you turn on Enable DQS
Mode in the controller settings tab.
When turned on, the postamble logic is used. If the
postamble logic is not used, there is a possibility of data loss
in the last transfer of each read burst.
Turn on to use the postamble logic. Turn off to remove the
the postamble logic you may see data loss in the last transfer
of each burst read. If you turn off this option, you must
ensure the read capture occurs correctly.
When turned on, the doing_rd_delayed signal is
generated using the positive edge of the system clock and
when turned off, doing_rd_delayed is generated using
the negative edge of the system clock. Turn on when the
negative edge of the system clock is too close to the positive
edge of the postamble clock. Refer to “Intermediate
The number of cycles of delay to allow for round-trip delay.
? March 2009 Altera Corporation
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相关代理商/技术参数 |
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| IP-RSENC | 功能描述:开发软件 Reed-Solomon Encoder MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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