- 您现在的位置：买卖IC网 > PDF目录16077 > IPR-SDRAM/DDR2 (Altera)IP DDR2 SDRAM CONTROLLER RENEW PDF资料下载
参数资料
| 型号： | IPR-SDRAM/DDR2 |
| 厂商： | Altera |
| 文件页数： | 60/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR2 SDRAM CONTROLLER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR2 SDRAM 控制器 |
| 许可证： | 续用许可证 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页当前第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页
3–24
Chapter 3: Functional Description
Interfaces & Signals
2. The user logic requests a write, a read, and another write request, which are
accepted.
3. The controller asserts the write data request signal to ask the user logic to present
valid write data and byte enables on the next clock edge.
4. The read data from the first read request is returned and marked as valid by the
read data valid signal.
5. The controller again asserts the write data request for the second write request.
6. The read data from the second read request is returned.
User Refresh Control
when the controller issues refreshes to the memory. This feature allows better control
of worst case latency and allows refreshes to be issued in bursts to take advantage of
idle periods.
Figure 3–16. User Refresh Control
clk
reset_n
Local Interface
local_refresh_req
local_refresh_ack
DDR SDRAM Interface
[1]
[2] [3]
[4]
ddr_cs_n
FF
00
FF
00
FF
00
FF
ddr_cke
FF
ddr_a
ddr_ba
0000
0400
0
0000
DDR Command
NOP
PCH NOP ARF
NOP
ARF
NOP
ddr_ras_n
ddr_cas_n
ddr_we_n
(1) DDR Command shows the command that the command signals are issuing.
1. The user logic asserts the refresh request signal to indicate to the controller that it
should perform a refresh. The state of the read and write requests signal does not
matter as the controller gives priority to the refresh request (although it completes
any currently active reads or writes).
2. The controller asserts the refresh acknowledge signal to indicate that it has issued
a refresh. This signal is still available even if the user refresh control option is not
switched on, allowing the user logic to keep track of when the controller is issuing
refreshes.
3. The user logic keeps the refresh request signal asserted to indicate that it wishes to
perform another refresh request.
The controller again asserts the refresh acknowledge signal to indicate that it has
issued a refresh. At this point the user logic deasserts the refresh request signal and
the controller continues with the reads and writes in its buffers.
? March 2009 Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| GEM31DTBN-S189 | CONN EDGECARD 62POS R/A .156 SLD |
| GEM31DTBH-S189 | CONN EDGECARD 62POS R/A .156 SLD |
| GEM31DTBD-S189 | CONN EDGECARD 62POS R/A .156 SLD |
| GEM31DTAN-S189 | CONN EDGECARD 62POS R/A .156 SLD |
| 10YXJ2200M10X20 | CAP ALUM 2200UF 10V 20% RADIAL |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IP-RSENC | 功能描述:开发软件 Reed-Solomon Encoder MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SLITE2 | 功能描述:开发软件 SerialLite II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
发布紧急采购，3分钟左右您将得到回复。