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| 型号： | IPR-SDRAM/DDR2 |
| 厂商： | Altera |
| 文件页数： | 40/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR2 SDRAM CONTROLLER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR2 SDRAM 控制器 |
| 许可证： | 续用许可证 |
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Chapter 3: Functional Description
Device-Level Description
All megafunctions in a device time out simultaneously when the most restrictive
evaluation time is reached. If there is more than one megafunction in a design, a
specific megafunction’s time-out behavior may be masked by the time-out behavior
of the other megafunctions.
For MegaCore functions, the untethered time-out is 1 hour; the tethered time-out
value is indefinite.
Your design stops working after the hardware evaluation time expires and the
local_ready output goes low.
For more information on OpenCore Plus hardware evaluation, refer to “OpenCore
Device-Level Description
This section describes the following topics:
■
■
■
■
■
Datapath
In Stratix series, the DDR and DDR2 SDRAM controllers use input-output element
(IOE) registers in the write and the read direction. In the read direction, the phase
shift reference circuit provides a process, voltage, temperature (PVT) compensated
delay on each DQS that is used to sample the DQ read data. In Cyclone series, the
DDR SDRAM controller uses carefully placed logic element (LE) registers to
guarantee consistent timing across DQS groups. An appropriate DQS delay is
produced by the Cyclone series programmable delay, the value of which is set by the
constraints script.
In the read direction, the double-rate data from the DQ pins are fed into positive and
a negative edge-triggered registers to sample data on both edges of DQS. These
signals are then passed through another set of configurable registers to return them to
the system clock domain. The IP Toolbench timing analysis configures the transition
from the DQS clock domain to the system clock domain (resynchronization). The
options range from using the positive edge of the system clock as your
resynchronization clock to more complex cases that require one or more extra sets of
registers to safely return your read data to the system clock domain.
f
For more information on resynchronization, refer to “Resynchronization” on
? March 2009 Altera Corporation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IP-RSENC | 功能描述:开发软件 Reed-Solomon Encoder MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SLITE2 | 功能描述:开发软件 SerialLite II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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