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| 型号： | IPR-SDRAM/DDR2 |
| 厂商： | Altera |
| 文件页数： | 75/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR2 SDRAM CONTROLLER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR2 SDRAM 控制器 |
| 许可证： | 续用许可证 |
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Chapter 3: Functional Description
Parameters
Table 3–19. Device Datasheet Settings (Part 2 of 2)
3–39
Parameter
t DQSS
t DQSS
Units
cycle
cycle
Description
The minimum write command to first DQS latching transition.
The maximum write command to first DQS latching transition.
Board Timings
Table 3–20. Pin Loading
Parameter
Manual pin load control
Pin loading on FPGA DQ/DQS pins
Pin loading on FPGA
address/command pins
Pin loading on FPGA clock pins
Units
On or off
pF
pF
pF
Description
Turn on or turn off the manual pin load control.
The default capacitive loading on the FPGA DQ/DQS pins is based
on the chosen memory type. You should update this figure if it does
not match your board and memory devices.
The default capacitive loading on the FPGA address/command pins
is based on the chosen memory type. You should update this figure
if it does not match your board and memory devices.
The default capacitive loading on the FPGA clock pins is based on
the chosen memory type. You should update this figure if it does
not match your board and memory devices.
perform timing analysis.
Table 3–21. Board Trace Delays
Parameter
FPGA clock output to memory chip clock
input, nominal delay
Memory DQ/DQS outputs to FPGA inputs,
nominal delay
Fed-back clock trace, nominal delay
Tolerance on nominal board delays ±
Worst trace skew between DQS/DQ/DM in
any one data group
Units
ps
ps
ps
%
ps
Description
The nominal or average value of the delay attributable to the board
traces from the FPGA clock output pin to the memory device clock
input pin.
The nominal or average value of the delay attributable to the board
traces from the memory device DQS and DQ clock output pins to the
FPGA input pins in read mode.
The nominal or average value of the delay attributable to the board
traces from the FPGA clock output pin to the fed-back clock input
pin. This delay should match the sum of the clock and DQ/DQS trace
lengths.
The tolerance on the nominal board trace delays. This tolerance
should take into account any variability between individual boards,
due to temperature or voltage, and different trace lengths to different
memory devices in your system.
The worst case skew with respect to DQS and any other DQ or DM
signal in any one byte group between any one memory device and
the FPGA.
? March 2009
Altera Corporation
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