参数资料
型号: IPR-SDRAM/DDR2
厂商: Altera
文件页数: 86/106页
文件大小: 0K
描述: IP DDR2 SDRAM CONTROLLER RENEW
标准包装: 1
系列: *
类型: MegaCore
功能: DDR2 SDRAM 控制器
许可证: 续用许可证
A–8
Resynchronization
Figure A–4 shows the resynchronization registers for Stratix II devices with fed-back
capture (refer to Table 3–15 on page 3–35 ).
Figure A–4. Resynchronization Registers—Stratix II Devices with Fed-back Capture
Fed-back PLL
(Optional)
capture_clk
Intermediate resynchronization registers
local_rdata
(see Note 1)
Capture registers
DQ
PLL
clk
resynch_clk
Reclock resynchronized data
Resynchronization registers
to rising edge registers
(see Note 2)
Clocked by Capture Clock
Clocked by Resynchronization Clock
Clocked by System Clock
Notes to Figure A–4 :
(1) IP Toolbench automatically inserts the intermediate resynchronization registers, depending on your choice of resynchronization phase.
(2) IP Toolbench automatically inserts these registers if the design needs them.
? March 2009 Altera Corporation
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