- 您现在的位置：买卖IC网 > PDF目录16077 > IPR-SDRAM/DDR2 (Altera)IP DDR2 SDRAM CONTROLLER RENEW PDF资料下载
参数资料
| 型号： | IPR-SDRAM/DDR2 |
| 厂商： | Altera |
| 文件页数： | 41/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR2 SDRAM CONTROLLER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR2 SDRAM 控制器 |
| 许可证： | 续用许可证 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页当前第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页
Chapter 3: Functional Description
3–5
Device-Level Description
In the write direction, the wdata_valid signal acts as an enable on the
local_wdata registers. The output of these registers is clocked into registers in the
IOE where it is fed to the DQ pins. The registers in the IOE are clocked by the write
clock (which is 90° before the system clock) so that DQS, which is generated by the
datapath, appears in the center of the data on the DQ pins. The write DQS is
generated from registers clocked by the system clock so that the t DQSS parameter is met
at the DDR or DDR2 SDRAM device.
Table 3–3. Datapath Interface
Signal name
control_doing_wr
control_wdata_valid
control_dqs_burst
control_wdata[]
control_be[]
control_doing_rd
control_rdata[]
Direction
Input
Input
Input
Input
Input
Input
Output
Description
The control_doing_wr signal is asserted when the controller is
writing to the DDR or DDR2 SDRAM and controls the output enables on
the DQ pins.
The control_wdata_valid signal is a registered version of the
write data request to the local interface. It enables the write data and
byte enable registers so that they are only updated when valid data and
enables are available.
The control_dqs_burst signal controls the output enables of the
DQS pins. The DQS output enable must be asserted for longer than the
DQ output enable, particularly when the local burst size is shorter than
the memory burst length.
The control_wdata signal is the write data bus and should have
valid data in the same clock cycle that control_wdata_valid is
asserted.
The control_be signal is the byte enable bus and should have valid
data in the same clock cycle that control_wdata_valid is
asserted. The byte enables are converted into DDR or DDR2 SDRAM
data mask signals.
The control_doing_rd signal is asserted when the controller is
reading from the DDR or DDR2 SDRAM and enables the DQ capture
registers. It also controls the postamble control registers to prevent the
DQ capture registers from being inadvertently clocked after the DQS
read postamble.
The control_rdata bus is the read data bus and has valid data
some clock cycles after the read command is issued. The exact
relationship depends on the CAS latency of the memory and whether or
not registered DIMMs are being used.
? March 2009
Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| GEM31DTBN-S189 | CONN EDGECARD 62POS R/A .156 SLD |
| GEM31DTBH-S189 | CONN EDGECARD 62POS R/A .156 SLD |
| GEM31DTBD-S189 | CONN EDGECARD 62POS R/A .156 SLD |
| GEM31DTAN-S189 | CONN EDGECARD 62POS R/A .156 SLD |
| 10YXJ2200M10X20 | CAP ALUM 2200UF 10V 20% RADIAL |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IP-RSENC | 功能描述:开发软件 Reed-Solomon Encoder MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SLITE2 | 功能描述:开发软件 SerialLite II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
发布紧急采购，3分钟左右您将得到回复。