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参数资料
| 型号： | IPR-SDRAM/DDR2 |
| 厂商： | Altera |
| 文件页数： | 27/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR2 SDRAM CONTROLLER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR2 SDRAM 控制器 |
| 许可证： | 续用许可证 |
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Chapter 2: Getting Started
MegaWizard Plug-In Manager Design Flow
Table 2–1. Generated Files (Part 2 of 2)
Filename
(Note 1) (2)
Description
2–17
remove_constraints_for_ <variation name> .tcl
top_ddr_settings.txt
top_pre_compile_ddr_timing_summary.txt
verify_timing_for_ <variation name> .tcl
The remove constraints script for the variation.
Critical settings file that stores the custom variation’s
parameters. IP Toolbench uses this file to generate the add
constraints script. The verify timing script and the DDR Timing
Wizard also read this file.
Log file that stores the results of the precompilation system
timing analysis.
The verify timing script.
(1) <project name> is the name of the Quartus II project top-level entity.
(2) <variation name> is the name you give to the controller you create with the Megawizard.
2. After you review the generation report, click Exit to close IP Toolbench.
1
The Quartus II IP File ( .qip ) is a file generated by the MegaWizard interface or SOPC
Builder that contains information about a generated IP core. You are prompted to add
this .qip file to the current Quartus II project at the time of file generation. In most
cases, the .qip file contains all of the necessary assignments and information required
to process the core or system in the Quartus II compiler. Generally, a single .qip file is
generated for each MegaCore function and for each SOPC Builder system. However,
some more complex SOPC Builder components generate a separate .qip file, so the
system .qip file references the component .qip file.
You have finished the walkthrough. Now, simulate the example design (see
Simulate the Example Design
You can simulate the example design with the IP Toolbench-generated IP functional
simulation models. IP Toolbench generates a VHDL or Verilog HDL testbench for
your example design, which is in the testbench directory in your project directory.
f
You can use the IP functional simulation model with any Altera-supported VHDL or
Verilog HDL simulator. The instructions for the ModelSim simulator are different to
other simulators.
Simulating With the ModelSim Simulator
To simulate the example design with the ModelSim ? simulator, follow these steps:
1. Obtain a memory model that matches your chosen parameters and save it to the
< directory name > testbench directory. For example, you can download a Micron
memory model from the Micron web site at www.micron.com .
? March 2009
Altera Corporation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IP-RSENC | 功能描述:开发软件 Reed-Solomon Encoder MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SLITE2 | 功能描述:开发软件 SerialLite II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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