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参数资料
| 型号： | MT48V8M16LFB4-75M:G |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| 封装： | 8 X 8 MM, LEAD FREE, VFBGA-54 |
| 文件页数： | 16/80页 |
| 文件大小： | 2775K |
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PDF: 09005aef807f4885/Source: 09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
23
2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
Register Definition
Commands
Table 8 provides a quick reference of available commands. This is followed by a written
description of each command. Three additional Truth Tables appear following the Oper-
ation section; these tables provide current state/next state information.
Notes:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0–A11 provide row address, and BA0, BA1 determine which bank is made active.
3. A0–A8 (x16) or A0–A7 (x32) provide column address; A10 HIGH enables the auto precharge
feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1
determine which bank is being read from or written to.
4. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged
and BA0, BA1 are “Don’t Care.”
5. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
6. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
for CKE.
7. A0–A10 define the op-code written to the mode register. BA0–BA1 either select mode regis-
ter or the extended mode register (BA0 = BA1 = 0 select the mode register, BA1 = 1, BA0 = 0
selects the extended mode register, all other combinations of BA0-BA1 are reserved).
8. Activates or deactivates the DQ during WRITEs (0-clock delay) and READs (2-clock delay). For
x16, LDQM controls DQ0–DQ7, and UDQM controls DQ8–DQ15. For x32, DQM0 controls
DQ0–DQ7, DQM1 controls DQ8–DQ15, DQM2 controls DQ16–23, and DQM3 controls DQ24–
DQ31.
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from being executed by the
SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese-
lected. Operations already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected SDRAM to
perform a NOP (RAS#, CAS#, and WE# are HIGH, and CS# is LOW). This prevents
unwanted commands from being registered during idle or wait states. Operations
already in progress are not affected.
Table 8:
Truth Table – Commands and DQM Operation
Note 1 applies to entire table
Name (Function)
CS#
RAS# CAS#
WE#
DQM
Addr
DQ
Notes
COMMAND INHIBIT (NOP)
H
XXXX
X
NO OPERATION (NOP)
LHHH
X
ACTIVE (Select bank and activate row)
L
H
X
Bank/row
X
READ (Select bank and column, and start READ burst)
L
H
L
H
L/H8
Bank/col
X
WRITE (Select bank and column, and start WRITE burst)
L
H
L
L/H8
Bank/col
Valid
BURST TERMINATE
LHH
L
X
Active
PRECHARGE (Deactivate row in bank or banks)
L
H
L
X
Code
X
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LL
LH
X
LOAD MODE REGISTER
L
LLL
X
Op-code
X
Write enable/output enable
–
–––L
–
Active
Write inhibit/output High-Z
–
–––
H
–
High-Z
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相关代理商/技术参数 |
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|---|---|
| MT48V8M16LFB4-8 ITG | 制造商:Micron Technology Inc 功能描述:DRAM Chip Mobile SDRAM 128M-Bit 8Mx16 2.5V 54-Pin VFBGA Tray |
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