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参数资料
| 型号： | MT48V8M16LFB4-75M:G |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| 封装： | 8 X 8 MM, LEAD FREE, VFBGA-54 |
| 文件页数： | 40/80页 |
| 文件大小： | 2775K |
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PDF: 09005aef807f4885/Source: 09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
45
2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
READs
Notes:
after tXSR has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted; that is, the current state is for a specific
bank and the commands shown are those allowed to be issued to that bank when in that
state. Exceptions are covered in the notes below.
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank. COM-
MAND INHIBIT or NOP commands or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other
bank are determined by its current state and Table 10 and according to Table 11 on
Table 10:
Truth Table – Current State Bank n, Command to Bank n
Notes 1–6 apply to entire table; notes appear below table
Current
State
CS#
RAS# CAS# WE# Command (Action)
Notes
Any
H
XXX
COMMAND INHIBIT (NOP/Continue previous operation)
L
HHH
NO OPERATION (NOP/Continue previous operation)
Idle
L
H
ACTIVE (Select and activate row)
LLL
H
AUTO REFRESH
LLLL
LOAD MODE REGISTER
LL
H
L
PRECHARGE
Row active
LH
READ (Select column and start READ burst)
LH
L
WRITE (Select column and start WRITE burst)
LL
H
L
PRECHARGE (Deactivate row in bank or banks)
Read (auto
precharge
disabled)
LH
READ (Select column and start new READ burst)
LH
L
WRITE (Select column and start WRITE burst)
LL
H
L
PRECHARGE (Truncate READ burst, start PRECHARGE)
LH
H
L
BURST TERMINATE
Write (auto
precharge
disabled)
LH
READ (Select column and start READ burst)
LH
L
WRITE (Select column and start new WRITE burst)
LL
H
L
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
LH
H
L
BURST TERMINATE
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not
yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
Precharging: Starts with registration of a PRECHARGE command and ends when
tRP is met. After tRP is met, the bank will be in the idle state.
Row activating: Starts with registration of an ACTIVE command and ends when tRCD
is met. After tRCD is met, the bank will be in the row active state.
Read w/auto
precharge enabled:
Starts with registration of a READ command with auto precharge
enabled and ends when tRP has been met. AFter tRP is met, the bank
will be in the idle state.
Write w/auto
precharge enabled:
Starts with registration of a WRITE command with auto precharge
enabled and ends when tRP has been met. After tRP is met, the bank
will be in the idle state.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48V8M16LFB4-8 ITG | 制造商:Micron Technology Inc 功能描述:DRAM Chip Mobile SDRAM 128M-Bit 8Mx16 2.5V 54-Pin VFBGA Tray |
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