- 您现在的位置：买卖IC网 > PDF目录262949 > MT48V8M16LFB4-75M:G 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 PDF资料下载
参数资料
| 型号： | MT48V8M16LFB4-75M:G |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| 封装： | 8 X 8 MM, LEAD FREE, VFBGA-54 |
| 文件页数： | 36/80页 |
| 文件大小： | 2775K |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页当前第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页
PDF: 09005aef807f4885/Source: 09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
41
2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
READs
Burst Read/Single Write
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the
access of a single column location (burst of 1), regardless of the programmed burst
length. READ commands access columns according to the programmed burst length
and sequence, just as in the normal mode of operation (M9 = 0).
Figure 30:
Clock Suspend During READ Burst
Notes:
1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW.
CONCURRENT Auto Precharge
An access command (READ or WRITE) to another bank while an access command with
auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM
supports concurrent auto precharge. Micron SDRAMs support concurrent auto
precharge. Four cases where concurrent auto precharge occurs are defined below.
READ with Auto Precharge
Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
rupt a READ on bank n, CL later. The precharge to bank n will begin when the READ
to bank m is registered (Figure 31 on page 42).
Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a READ on bank n when registered. DQM should be used 2 clocks prior to
the WRITE command to prevent bus contention. The precharge to bank n will begin
when the WRITE to bank m is registered (Figure 32 on page 42).
DON’T CARE
CLK
DQ
DOUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
NOP
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
CKE
INTERNAL
CLOCK
NOP
TRANSITIONING DATA
相关PDF资料 |
PDF描述 |
|---|---|
| MS8256FKXA-12 | 256K X 8 MULTI DEVICE SRAM MODULE, 120 ns, DMA32 |
| MT46V32M16BN-75IT | 32M X 16 DDR DRAM, 0.75 ns, PBGA60 |
| MT46V32M16P-6T | 32M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| MT28F644W18FE-705KTET | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA56 |
| MPAT-122128-1003MS | 12200 MHz - 12750 MHz RF/MICROWAVE FIXED ATTENUATOR, 2.2 dB INSERTION LOSS-MAX |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48V8M16LFB4-8 ITG | 制造商:Micron Technology Inc 功能描述:DRAM Chip Mobile SDRAM 128M-Bit 8Mx16 2.5V 54-Pin VFBGA Tray |
发布紧急采购，3分钟左右您将得到回复。