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参数资料
| 型号： | MT48V8M16LFB4-75M:G |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| 封装： | 8 X 8 MM, LEAD FREE, VFBGA-54 |
| 文件页数： | 27/80页 |
| 文件大小： | 2775K |
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PDF: 09005aef807f4885/Source: 09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
33
2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
READs
Figure 18:
READ-to-PRECHARGE
Notes:
1. Assumes tRAS(MIN) has been satisfied prior to the PRECHARGE command.
2. N + 3 is either the last data element of a BL = 4 or the last desired data element of a longer
burst.
3. DQM is LOW.
Full-page READ bursts can be truncated with the BURST TERMINATE command, and
fixed-length READ bursts may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at which the last desired data element is
valid, where x = CL - 1. This is shown in Figure 19 on page 34 for each possible CL; data
element n + 3 is the last desired data element of a longer burst.
CLK
DQ
DOUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
PRECHARGE
ACTIVE
t RP
T7
CLK
DQ
DOUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
PRECHARGE
ACTIVE
t RP
T7
CLK
DQ
DOUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK a,
COL n
NOP
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
PRECHARGE
ACTIVE
t RP
T7
BANK a,
ROW
BANK
(a or all)
DON’T CARE
X = 0 cycles
CL = 1
X = 1 cycle
CL = 2
CL = 3
BANK a,
COL n
BANK a,
ROW
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
BANK
(a or all)
X = 2 cycles
TRANSITIONING DATA
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48V8M16LFB4-8 ITG | 制造商:Micron Technology Inc 功能描述:DRAM Chip Mobile SDRAM 128M-Bit 8Mx16 2.5V 54-Pin VFBGA Tray |
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