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参数资料
| 型号： | MT48V8M16LFB4-75M:G |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| 封装： | 8 X 8 MM, LEAD FREE, VFBGA-54 |
| 文件页数： | 25/80页 |
| 文件大小： | 2775K |
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PDF: 09005aef807f4885/Source: 09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
31
2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
READs
Figure 16:
READ-to-WRITE
Notes:
1. CL = 3 is used for illustration.
2. The READ command may be to any bank, and the WRITE command may be to any bank.
3. If a burst of 1 is used, then DQM is not required.
The DQM input is used to avoid I/O contention, as shown in Figure 16 and Figure 17.
The DQM signal must be asserted (HIGH) at least 2 clocks prior to the WRITE command
(DQM latency is 2 clocks for output buffers) to suppress data-out from the READ. After
the WRITE command is registered, the DQ will go High-Z (or remain High-Z), regardless
of the state of the DQM signal, provided the DQM was active on the clock just prior to
the WRITE command that truncated the READ command. If not, the second WRITE will
be an invalid WRITE. For example, if DQM was LOW during T4 in Figure 17, then the
WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid.
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
0 clocks for input buffers) to ensure that the written data is not masked. Figure 16 shows
the case where the clock frequency allows for bus contention to be avoided without
adding a NOP cycle, and Figure 17 shows the case where the additional NOP is needed.
Figure 17:
READ-to-WRITE with Extra Clock Cycle
Notes:
1. CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE com-
mand may be to any bank.
DON’T CARE
READ
NOP
WRITE
NOP
CLK
T2
T1
T4
T3
T0
DQM
DQ
DOUT n
COMMAND
DIN b
ADDRESS
BANK,
COL n
BANK,
COL b
DS
tHZ
t
tCK
TRANSITIONING DATA
DON’T CARE
READ
NOP
DQM
CLK
DQ
DOUT n
T2
T1
T4
T3
T0
COMMAND
ADDRESS
BANK,
COL n
WRITE
DIN b
BANK,
COL b
T5
DS
tHZ
t
TRANSITIONING DATA
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48V8M16LFB4-8 ITG | 制造商:Micron Technology Inc 功能描述:DRAM Chip Mobile SDRAM 128M-Bit 8Mx16 2.5V 54-Pin VFBGA Tray |
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