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参数资料
| 型号： | MT48V8M16LFB4-75M:G |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| 封装： | 8 X 8 MM, LEAD FREE, VFBGA-54 |
| 文件页数： | 60/80页 |
| 文件大小： | 2775K |
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PDF: 09005aef807f4885/Source: 09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
63
2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
Timing Diagrams
Figure 42:
Self Refresh Mode
Notes:
1. No maximum time limit for self refresh. tRAS (MAX) only applies to non-self refresh mode.
2. tXSR requires a minimum of 2 clocks regardless of frequency or timing.
3. As a general rule, any time self refresh is exited, the DRAM may not reenter the self refresh
mode until all rows have been refreshed via the AUTO REFRESH command at the distrib-
uted refresh rate, (tREF/number of rows), or faster. However, the following exception is
allowed. Self refresh mode may be reentered any time after exiting if the following condi-
tions are all met:
3a. The DRAM has been in the self refresh mode for a minimum of 64ms prior to exiting.
3b. tXSR has not been violated.
3c. At least two AUTO REFRESH commands are performed during each 15.625s interval
while the DRAM remains out of the self refresh mode. See Table 17 on page 53.
4. Self refresh is not supported on automotive temperature (AT) devices.
DON’T CARE
tCH
tCL
tCK
tRP
CKE
CLK
DQ
Enter self refresh mode
Precharge all
active banks
tXSR2
CLK stable prior to exiting
self refresh mode
Exit self refresh mode
(Restart refresh time base)
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COMMAND
tCMH
tCMS
AUTO
REFRESH
PRECHARGE
NOP
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BA0, BA1
BANK(S)
High-Z
tCKS
AH
AS
AUTO
REFRESH
> tRAS1
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tCKH
tCKS
DQMU, DQML
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A0–A9, A11
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ALL BANKS
SINGLE BANK
A10
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T0
T1
T2
Tn + 1
To + 1
To + 2
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48V8M16LFB4-8 ITG | 制造商:Micron Technology Inc 功能描述:DRAM Chip Mobile SDRAM 128M-Bit 8Mx16 2.5V 54-Pin VFBGA Tray |
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