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参数资料
| 型号： | MT48V8M16LFB4-75M:G |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| 封装： | 8 X 8 MM, LEAD FREE, VFBGA-54 |
| 文件页数： | 43/80页 |
| 文件大小： | 2775K |
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PDF: 09005aef807f4885/Source: 09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
48
2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
READs
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. Concurrent auto precharge: Bank n will initiate the auto precharge command when its
burst has been interrupted by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the READ on bank n, CL later (see Figure 14 on
page 29).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank m will interrupt the READ on bank n when registered (see
Figure 16 and Figure 17 on page 31). DQM should be used one clock prior to the WRITE
command to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the WRITE on bank n when registered (see
Figure 24 on page 37) with the data-out appearing CL later. The last valid WRITE to bank n
will be data-in registered 1 clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank will interrupt the WRITE on bank n when registered (see
Figure 22 on page 36). The last valid WRITE to bank n will be data-in registered 1 clock prior
to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the READ on bank n, CL later. The PRECHARGE to bank n
will begin when the READ to bank m is registered (see Figure 31 on page 42).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be
used 2 clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to
bank n will begin when the WRITE to bank m is registered (see Figure 32 on page 42).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out
appearing CL later. The PRECHARGE to bank n will begin after tWR is met, where tWR
begins when the READ to bank m is registered. The last valid WRITE bank n will be data-in
registered 1 clock prior to the READ to bank m (see Figure 33 on page 43).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE
to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is reg-
istered. The last valid WRITE to bank n will be data registered 1 clock to the WRITE to bank
m (see Figure 34 on page 43).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48V8M16LFB4-8 ITG | 制造商:Micron Technology Inc 功能描述:DRAM Chip Mobile SDRAM 128M-Bit 8Mx16 2.5V 54-Pin VFBGA Tray |
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