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参数资料
| 型号： | MT48V8M16LFB4-75M:G |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| 封装： | 8 X 8 MM, LEAD FREE, VFBGA-54 |
| 文件页数： | 53/80页 |
| 文件大小： | 2775K |
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PDF: 09005aef807f4885/Source: 09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
57
2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
Notes
1. All voltages are referenced to Vss.
2. This parameter is sampled. VDD, VDDQ = +3.3V; TA = 25°C; pin under test biased at
1.4V, f = 1 MHz.
3. IDD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range is ensured (0°C ≤ TA ≤ +70°C (commercial), –
40°C ≤ TA ≤ +85°C (industrial), and –40°C ≤ TA ≤ +105°C (automotive)).
6. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be pow-
ered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO
REFRESH command wake-ups should be repeated any time the tREF refresh require-
ment is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must tran-
sit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured at 1.5V (for LC devices) or at 1.25V (V devices) with equivalent
load:
10. tHZ defines the time at which the output achieves the open circuit condition; it is not
a reference to VOH or VOL. The last valid data element will meet tOH before going
High-Z.
11. AC timing and IDD tests use established values for VIL and VIH, with timing referenced
to VIH/2 crossover point. If the input transition time is longer than 1ns, then the tim-
ing is referenced at VIL(MAX) and VIH(MIN) and no longer at the VIH/2 crossover point.
Established tester values follow: VIL = 0V, VIH = 3.0V for LC devices and VIH = 2.3V for V
devices.
12. Other input signals are allowed to transition no more than once every 2 clocks and are
otherwise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum
cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at
minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent on any
timing parameter.
18. The IDD current will increase or decrease proportionally according to the amount of
frequency alteration for the test condition.
19. Address transitions average one transition every 2 clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on tCK = 125MHz for -8 and tCK = 100MHz for -10.
Q
30pF
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48V8M16LFB4-8 ITG | 制造商:Micron Technology Inc 功能描述:DRAM Chip Mobile SDRAM 128M-Bit 8Mx16 2.5V 54-Pin VFBGA Tray |
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