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参数资料
| 型号： | MT48V8M16LFB4-75M:G |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| 封装： | 8 X 8 MM, LEAD FREE, VFBGA-54 |
| 文件页数： | 56/80页 |
| 文件大小： | 2775K |
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PDF: 09005aef807f4885/Source: 09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
6
2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
FBGA Part Marking Decoder
Figure 1:
128Mb SDRAM Part Numbers
Notes:
1. Not all speeds and configurations are available.
2. Contact Micron for availability.
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part
marking that is different from the part number. Micron’s new FBGA Part Marking
Decoder makes it easier to understand that part marking. Visit the Web site at
General Description
The Micron 128Mb SDRAM device is a high-speed CMOS, dynamic random access
memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM
with a synchronous interface (all signals are registered on the positive edge of the clock
signal, CLK). Each of the x16’s 33,554,432-bit banks is organized as 4,096 rows by 512
columns by 16 bits. Each of the x32’s 33,554,432-bit banks is organized as 4,096 rows by
256 columns by 32 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0–A11 select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8
locations, or the full page, with a burst terminate option. An auto precharge function
may be enabled to provide a self-timed row precharge that is initiated at the end of the
burst sequence.
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Configuration
MT48
Package
Speed
Temperature
Configuration
8 Meg x 16
4 Meg x 32
8M16
4M32
Package
54-ball VFBGA (8 x 8mm)
54-ball VFBGA (8 x 8mm) lead-free
90-ball VFBGA (8 x 13mm)
90-ball VFBGA (8 x 13mm) lead-free
54-pin TSOP II (400 mil)
54-pin TSOP II (400 mil) Lead-Free
IT
AT
Operating Temp
Standard
Industrial
Automotive
Example Part Number: MT48V4M32LFF5-10XT
Voltage (VDD/VDDQ)
3.3V/ 3.3V
2.5V / 2.5V–1.8V
LC
V
VDD/
VDDQ
LF
F4
B4
F5
B5
TG2
P2
Revision
:G
Rev
Revision
Speed Grade
tCK = 7.5ns, CL = 3
tCK = 8ns, CL = 3
tCK = 10ns, CL = 3
-75M2
-8
-102
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48V8M16LFB4-8 ITG | 制造商:Micron Technology Inc 功能描述:DRAM Chip Mobile SDRAM 128M-Bit 8Mx16 2.5V 54-Pin VFBGA Tray |
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