- 您现在的位置：买卖IC网 > PDF目录262949 > MT48V8M16LFB4-75M:G 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 PDF资料下载
参数资料
| 型号： | MT48V8M16LFB4-75M:G |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| 封装： | 8 X 8 MM, LEAD FREE, VFBGA-54 |
| 文件页数： | 8/80页 |
| 文件大小： | 2775K |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页
PDF: 09005aef807f4885/Source: 09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
16
2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
Register Definition
7. Wait at least tRP time; during this time, NOPs or DESELECT commands must be
given. All banks will complete their precharge, thereby placing the device in the all
banks idle state.
8. Issue an AUTO REFRESH command.
9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands
are allowed.
10. Issue an AUTO REFRESH command.
11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands
are allowed.
12. The SDRAM is now ready for mode register programming. Because the mode register
will power up in an unknown state, it should be loaded with desired bit values prior to
applying any operational command. Using the LMR command, program the mode
register. The mode register is programmed via the MODE REGISTER SET command
with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again
or the device loses power. Not programming the mode register upon initialization will
result in default settings, which may not be desired. Outputs are guaranteed High-Z
after the LMR command is issued. Outputs should be High-Z already before the LMR
command is issued.
13. Wait at least tMRD time, during which only NOP or DESELECT commands are
allowed.
14. Using the LMR command, program the extended mode register. The low-power
extended mode register is programmed via the MODE REGISTER SET command with
BA1 = 1, BA0 = 0 and retains the stored information until it is programmed again or
the device loses power. Not programming the extended mode register upon initializa-
tion will result in default settings for the low-power features. The extended mode will
default with the temperature sensor enabled, full drive strength, and full array refresh.
15. Wait at least tMRD time, during which only NOP or DESELECT commands are
allowed.
At this point, the DRAM is ready for any valid command.
Note:
If desired, more than two AUTO REFRESH commands can be issued in the sequence.
After steps 9 and 10 are complete, repeat them until the desired number of AUTO
REFRESH + tRFC loops is achieved.
Register Definition
Mode Register
To achieve low power consumption, there are two mode registers in the Mobile compo-
nent: mode register and extended mode register. Mode register is discussed in this
section. Extended mode register is discussed on page 21. The mode register is used to
define the specific mode of operation of the SDRAM. This definition includes the selec-
tion of BL, a burst type, CL, an operating mode, and a write burst mode, as shown in
Figure 7 on page 18. The mode register is programmed via the LOAD MODE REGISTER
command and will retain the stored information until it is programmed again or the
device loses power.
Mode register bits M0–M2 specify BL, M3 specifies the type of burst (sequential or inter-
leaved), M4–M6 specify CL, M7 and M8 specify the operating mode, M9 specify the write
burst mode (single or programmed burst length), M10 and M11 are reserved and must
be set to zero. To address the mode register, M12 and M13 must be set to zero.
相关PDF资料 |
PDF描述 |
|---|---|
| MS8256FKXA-12 | 256K X 8 MULTI DEVICE SRAM MODULE, 120 ns, DMA32 |
| MT46V32M16BN-75IT | 32M X 16 DDR DRAM, 0.75 ns, PBGA60 |
| MT46V32M16P-6T | 32M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| MT28F644W18FE-705KTET | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA56 |
| MPAT-122128-1003MS | 12200 MHz - 12750 MHz RF/MICROWAVE FIXED ATTENUATOR, 2.2 dB INSERTION LOSS-MAX |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48V8M16LFB4-8 ITG | 制造商:Micron Technology Inc 功能描述:DRAM Chip Mobile SDRAM 128M-Bit 8Mx16 2.5V 54-Pin VFBGA Tray |
发布紧急采购，3分钟左右您将得到回复。