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参数资料
| 型号： | MT48V8M16LFB4-75M:G |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| 封装： | 8 X 8 MM, LEAD FREE, VFBGA-54 |
| 文件页数： | 5/80页 |
| 文件大小： | 2775K |
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PDF: 09005aef807f4885/Source: 09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
13
2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
Pin/Ball Assignments and Descriptions
Table 4:
Ball Descriptions: 90-Ball VFBGA
90-Ball FBGA
Symbol
Type
Description
J1
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
J2
CKE
Input
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides precharge power-down and SELF
REFRESH operation (all banks idle), active power-down (row active in any
bank), or CLOCK SUSPEND operation (burst/access in progress). CKE is
synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CLK, are disabled during power-down
and self refresh modes, providing low standby power. CKE may be tied
HIGH.
J8
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH, but READ/WRITE bursts already in progress will continue and DQM
will retain its DQ mask capability while CS# remains HIGH. CS# provides
for external bank selection on systems with multiple banks. CS# is
considered part of the command code.
J9, K7, K8
RAS#, CAS#,
WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
K9, K1, F8, F2
DQM0–3
Input
Input/Output mask: DQM is sampled HIGH and is an input mask signal for
write accesses and an output enable signal for read accesses. Input data is
masked during a WRITE cycle. The output buffers are placed in a High-Z
state (2-clock latency) during a READ cycle. DQM0 corresponds to DQ0–
DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–
DQ23, and DQM3 corresponds to DQ24–DQ31. DQM0–3 are considered
same state when referenced as DQM.
J7, H8
BA0, BA1
Input
Bank address input(s): BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. These pins also
provide the op-code during a LOAD MODE REGISTER command.
G8, G9, F7, F3, G1, G2,
G3, H1, H2, J3, G7, H9
A0–A5
A6–A11
Input
Address inputs: A0–A11 are sampled during the ACTIVE command (row-
address A0–A11) and READ/WRITE command (column-address A0–A7;
with A10 defining auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine whether all banks are to be
precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address
inputs also provide the op-code during a LOAD MODE REGISTER
command.
R8, N7, R9, N8, P9, M8,
M7, L8, L2, M3, M2, P1,
N2, R1, N3, R2, E8, D7,
D8, B9, C8, A9, C7, A8,
A2, C3, A1, C2, B1, D2,
D3, E2
DQ0–DQ5
DQ6–DQ11
DQ12–DQ17
DQ18–DQ23
DQ24–DQ29
DQ30–DQ31
I/O
Data input/output: Data bus.
E3, E7, H3, H7, K2, K3
NC
–
No connect: These pins should be left unconnected. H3 is a no connect
for this part, but may be used as A12 in future designs.
B2, B7, C9, D9, E1, L1,
M9, N9, P2, P7
VDDQ
Supply DQ power: Isolated DQ power on the die to improve noise immunity.
B8, B3, C1, D1, E9, L9,
M1, N1, P3, P8
VSSQ
Supply DQ ground: Isolated DQ power on the die to improve noise immunity.
A7, F9, L7, R7
VDD
Supply Power supply: Voltage dependant on option.
A3, F1, L3, R3
VSS
Supply Ground.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48V8M16LFB4-8 ITG | 制造商:Micron Technology Inc 功能描述:DRAM Chip Mobile SDRAM 128M-Bit 8Mx16 2.5V 54-Pin VFBGA Tray |
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