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| 型号： | MT48V8M16LFB4-75M:G |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| 封装： | 8 X 8 MM, LEAD FREE, VFBGA-54 |
| 文件页数： | 55/80页 |
| 文件大小： | 2775K |
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PDF: 09005aef807f4885/Source: 09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
59
2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
Timing Diagrams
Figure 38:
Initialize and Load Mode Register
Notes:
1. The two AUTO REFRESH commands at T9 and T19 may be applied either before LOAD
MODE REGISTER (LMR) command.
2. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH
command, ACT = ACTIVE command, RA = row address, and BA = bank address.
3. The LOAD MODE REGISTER both for mode register and for extended mode register, and
two AUTO REFRESH commands can be in any order. However, all must occur prior to an
ACTIVE command.
4. Optional REFRESH command.
5. Although not required, to prevent bus contention, it is suggested to keep DQM HIGH dur-
ing the initialization sequence. See Table 17 on page 53.
CLK
tCK
T0
T1
T3
T5
T7
T9
T19
T29
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CKE
BA0, BA1
Load Extended
Mode Register
Load Mode
Register
tCKS
Power-up:
VDD and
CLK stable
T = 100s
tCKH
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DQML, DQMU5
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DQ
High-Z
A0–A9, A11
RA
A10
RA
ALL BANKS
LMR3
NOP
PRE
LMR3
AR
AR4
ACT
tCMS tCMH
BA0 = L,
BA1 = H
tAS tAH
tAS
tAH
BA0 = L,
BA1 = L
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CODE
tAS tAH
CODE
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PRE
ALL BANKS
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DON’T CARE
BA
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tRP
tMRD
tRP
tRFC
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COMMAND1,2
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相关代理商/技术参数 |
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|---|---|
| MT48V8M16LFB4-8 ITG | 制造商:Micron Technology Inc 功能描述:DRAM Chip Mobile SDRAM 128M-Bit 8Mx16 2.5V 54-Pin VFBGA Tray |
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