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参数资料
| 型号： | MT48V8M16LFB4-75M:G |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| 封装： | 8 X 8 MM, LEAD FREE, VFBGA-54 |
| 文件页数： | 20/80页 |
| 文件大小： | 2775K |
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PDF: 09005aef807f4885/Source: 09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
27
2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
READs
Figure 11:
Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK< 3
READs
READ bursts are initiated with a READ command, as shown in Figure 12.
The starting column and bank addresses are provided with the READ command, and
auto precharge is either enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the completion of the burst. For the
READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following CL after the READ command. Each subsequent data-out element
will be valid by the next positive clock edge. Figure 13 on page 28 shows general timing
for each possible CL setting.
Figure 12:
READ Command
CLK
T2
T1
T3
T0
t
COMMAND
NOP
ACTIVE
READ or
WRITE
T4
NOP
RCD
DON’T CARE
CS#
WE#
CAS#
RAS#
CKE
CLK
COLUMN
ADDRESS
x16: A0–A8
x32: A0–A7
A10
BA0,BA1
HIGH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
ADDRESS
A9, A11
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48V8M16LFB4-8 ITG | 制造商:Micron Technology Inc 功能描述:DRAM Chip Mobile SDRAM 128M-Bit 8Mx16 2.5V 54-Pin VFBGA Tray |
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