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参数资料
| 型号： | MT48V8M16LFB4-75M:G |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| 封装： | 8 X 8 MM, LEAD FREE, VFBGA-54 |
| 文件页数： | 9/80页 |
| 文件大小： | 2775K |
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PDF: 09005aef807f4885/Source: 09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
17
2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
Register Definition
The mode register must be loaded when all banks are idle, and the controller must wait
the specified time before initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
Burst Length (BL)
Read and write accesses to the SDRAM are burst oriented, with BL being programmable,
as shown in Figure 8 on page 20. BL determines the maximum number of column loca-
tions that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4,
or 8 locations are available for both the sequential and the interleaved burst types, and a
full-page burst is available for the sequential mode. The full-page burst is used in
conjunction with the BURST TERMINATE command to generate arbitrary burst lengths.
If a full page burst is not terminated at the end of the page, it could wrap to column zero
and continue.
Reserved states cannot be used because unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to BL is effectively
selected. All accesses for that burst take place within this block, meaning that the burst
will wrap within the block if a boundary is reached. The block is uniquely selected by A1–
A8 (x16) or A1–A7 (x32) when BL = 2; by A2–A8 (x16) or A2–A7 (x32) when BL = 4; and by
A3–A8 (x16) or A3–A7 (x32) when BL = 8. The remaining (least significant) address bit(s)
is (are) used to select the starting location within the block. Full-page bursts wrap within
the page if the boundary is reached.
Burst Type
Accesses within a given burst may be programmed either to be sequential or interleaved;
this is referred to as the burst type and is selected via bit M3. Note only a sequential burst
is allowed for full page bursts.
The ordering of accesses within a burst is determined by BL, the burst type, and the
starting column address, as shown in Table 6 on page 19.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48V8M16LFB4-8 ITG | 制造商:Micron Technology Inc 功能描述:DRAM Chip Mobile SDRAM 128M-Bit 8Mx16 2.5V 54-Pin VFBGA Tray |
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