15 Clock Timer (CT)
S1C17602 TECHNICAL MANUAL
EPSON
15-5
CT
15.5 Clock Timer Interrupts
The CT module includes functions for generating the following four kinds of interrupts:
32 Hz, 8 Hz, 2 Hz, 1 Hz interrupts
The CT module outputs a single interrupt signal shared by the above four interrupt factors to the interrupt controller
(ITC). The interrupt flag within the CT module should be read to identify the interrupt factor that occurred.
32 Hz, 8 Hz, 2 Hz, 1 Hz interrupts
Generated at the 32 Hz, 8 Hz, 2 Hz, and 1 Hz signal falling edges, these interrupt requests set the following
interrupt flags in the CT module to 1.
CTIF32: 32 Hz Interrupt Flag in the Clock Timer Interrupt Flag (CT_IFLG) Register (D3/0x5003)
CTIF8:
8 Hz Interrupt Flag in the Clock Timer Interrupt Flag (CT_IFLG) Register (D2/0x5003)
CTIF2:
2 Hz Interrupt Flag in the Clock Timer Interrupt Flag (CT_IFLG) Register (D1/0x5003)
CTIF1:
1 Hz Interrupt Flag in the Clock Timer Interrupt Flag (CT_IFLG) Register (D0/0x5003)
To use these interrupts, set the following interrupt enable bits to 1 for the corresponding interrupt flags. If the
interrupt enable bits are set to 0 (default), the interrupt flag will not be set to 1, and the interrupt requests for
this factor will not be sent to the ITC.
CTIE32: 32 Hz Interrupt Enable Bit in the Clock Timer Interrupt Mask (CT_IMSK) Register (D3/0x5002)
CTIE8:
8 Hz Interrupt Enable Bit in the Clock Timer Interrupt Mask (CT_IMSK) Register (D2/0x5002)
CTIE2:
2 Hz Interrupt Enable Bit in the Clock Timer Interrupt Mask (CT_IMSK) Register (D1/0x5002)
CTIE1:
1 Hz Interrupt Enable Bit in the Clock Timer Interrupt Mask (CT_IMSK) Register (D0/0x5002)
The CT module outputs an interrupt request to the ITC if the CTIF* is set to 1. This interrupt request signal sets
the clock timer interrupt flag inside the ITC to 1 and generates an interrupt if the ITC and S1C17 core interrupt
conditions are met.
Check the frequency of a clock timer interrupt by reading CTIF* as part of the clock timer interrupt processing
routine.
Note: To prevent interrupt recurrences, the CT module interrupt flag CTIF*must be reset within the
interrupt processing routine following a clock timer interrupt.
To prevent generating unnecessary interrupts, reset the corresponding CTIF* before
permitting clock timer interrupts from CTIE*.
Interrupt vectors
The clock timer interrupt vector numbers and vector addresses are listed below.
Vector number: 7 (0x07)
Vector address: TTBR + 0x1c
Other interrupt settings
The ITC allows the priority of clock timer interrupts to be set between level 0 (the default value) and level 7. To
generate actual interrupts, the PSR (S1C17 core internal processor status register) IE (interrupt enable) bit must
be set to 1.
For more information on interrupt processing, see “6 Interrupt Controller (ITC).”