18 UART
S1C17602 TECHNICAL MANUAL
EPSON
18-19
0x4104/0x4124: UART Ch.x Control Registers (UART_CTLx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
UART Ch.x
Control Register
(UART_CTLx)
0x4104
0x4124
(8 bits)
D7
–
reserved
–
0 when being read.
D6
REIEN
Receive error int. enable
1 Enable
0 Disable
0
R/W
D5
RIEN
Receive buffer full int. enable
1 Enable
0 Disable
0
R/W
D4
TIEN
Transmit buffer empty int. enable 1 Enable
0 Disable
0
R/W
D3–2
–
reserved
–
0 when being read.
D1
RBFI
Receive buffer full int. condition
1 2 bytes
0 1 byte
0
R/W
D0
RXEN
UART enable
1 Enable
0 Disable
0
R/W
The “x” in register names indicates the channel number (0 or 1).
0x4104: UART Ch.0 Control Register (UART_CTL0)
0x4124: UART Ch.1 Control Register (UART_CTL1)
D7
Reserved
D6
REIEN: Receive Error Interrupt Enable Bit
Permits interrupt requests to the ITC when a receive error occurs.
1 (R/W): Permitted
0 (R/W): Prohibited (default)
Set this bit to 1 to process receive errors using interrupts.
D5
RIEN: Receive Buffer Full Interrupt Enable Bit
Permits interrupt requests to the ITC caused when the received data quantity in the receive data buffer
reaches the quantity specified in RBFI (D1).
1 (R/W): Permitted
0 (R/W): Prohibited (default)
Set this bit to 1 to read receive data using interrupts.
D4
TIEN: Transmit Buffer Empty Interrupt Enable Bit
Permits interrupt requests to the ITC caused when transmission data in the transmit data buffer is sent
to the shift register (i.e. when data transmission begins).
1 (R/W): Permitted
0 (R/W): Prohibited (default)
Set this bit to 1 to program data to the transmit data buffer using interrupts.
D[3:2]
Reserved
D1
RBFI: Receive Buffer Full Interrupt Condition Setup Bit
Sets the quantity of data in the receive buffer to generate a receive buffer full interrupt.
1 (R/W): 2 bytes
0 (R/W): 1 byte (default)
If receive buffer full interrupts are permitted (RIEN = 1), the UART outputs an interrupt request pulse
to the ITC when the quantity of received data specified by RBFI is loaded into the receive data buffer.
If the RBFI bit is 0, an interrupt request pulse is output as soon as one item of received data is loaded
into the receive data buffer (when the RDRY flag (D1/UART_STx register) is set to 1). If RBFI is 1, an
interrupt request pulse is output as soon as two items of received data are loaded into the receive data
buffer (when the RD2B flag (D3/UART_STx register) is set to 1).
D0
RXEN: UART Enable Bit
Permits data transfer by the UART.
1 (R/W): Permitted
0 (R/W): Prohibited (default)
Set RXEN to 1 before starting UART transfers. Setting RXEN to 0 will stop data transfers. Set the
transfer conditions while RXEN is 0.
Preventing transfers by writing 0 to RXEN also clears transfer data buffers.
UART