24 A/D Converter (ADC10SA)
S1C17602 TECHNICAL MANUAL
EPSON
24-5
ADC10SA
1. External trigger (#ADTRG)
This type uses an input signal via the #ADTRG pin as a trigger.
To use this trigger type, the #ADTRG pin must be configured using the Port Function Select Register. This
type starts A/D conversion by detecting Low level #ADTRG signal.
2. 16-bit timer (T16) Ch.0
This type uses an underflow signal of 16-bit timer (T16) Ch.0 as a trigger. The type is effective when
periodic A/D conversion is required because the cycle of the signal can be configured programmably by the
timer. For settings for the timer, refer to “11 16-bit Timer (T16).”
3. Software trigger
This type uses the software’s writing 1 to ADCTL (D1/AD_CTL register) as a trigger to start A/D
conversion.
*
ADCTL: A/D Conversion Control/Status Bit in the ADC10 Control/Status (ADC10_CTL) Register
(D1/0x5382)
Setting of sampling time
This A/D converter provides ADST[2:0] (D[2:0]/ADC10_TRG register) enabling the input sampling time of
analog signals to be configured to 8 steps (2 to 9 of the conversion clock).
ADST[2:0]: Sampling Clock Count Bits in the ADC10 Control/Status (AD_CTL) Register (D[2:0]/0x5382)
The sampling time must satisfy the time required for acquiring input voltage (tACQ, acquisition time). Figure
24.3.1 shows the equivalent circuit for the analog input. Configure fADC, ADST[2:0] so that tACQ satisfies the
following expression.
Rs: Source impedance
RAIN: Analog input resistance
CAIN: Analog input capacitance
CAIN
RAIN
RS
VDD
VSS
Figure 24.3.1: Equivalent circuit for analog input
tACQ = 8 × (RS + RAIN) × CAIN
1 × (Sampling time set by ADST[2:0]) > tACQ
fADC:A/D conversion clock
FADC
Setting of conversion result storage mode
After completing A/D conversion, this 10-bit A/D converter stores the 10-bit conversion result in the A/D
conversion result storage register ADD[15:0] (D[15:0]/ADC10_ADD register).
ADD[15:0]: A/D Converted Data Bits in the ADC10 Conversion Result (ADC10_ADD) Register (D[15:0]/
0x5380)
The conversion result storage mode can configure STMD (D[7]/ADC10_TRG register), and select either high-
order or low-order to store 10-bit A/D conversion result in ADD[15=0].
STMD: Converted Data Store Mode Bits in the ADC10 Trigger/Channel Select (ADC10_TRG) Register
(D[7]/0x5382)
STMD=0: ADD[15:10]=0, ADD[9]= conversion result [MSB], ADD[0]= conversion result [LSB]
STMD=1: ADD[15]=[MSB], ADD[6]= conversion result [LSB], ADD[5:0]=0