24 A/D Converter (ADC10SA)
24-16
EPSON
S1C17602 TECHNICAL MANUAL
After completion of A/D conversion, if the conversion data is stored to ADD(D[15:0]/ADC10_ADD
register) it is set to 1. At that time, if the ADCIE(D4/ADC10_CTL register) is set to 1, conversion
completion interruption request signal for ITC is output. If interruption conditions of ITC and S1C17
core are valid, interruption will be occurred.
It is reset to 0 by reading ADD.
When multiple channels make A/D conversion, if next A/D conversion is finished in the status where
ADCF is 1 (before reading conversion data), data register overwrites to the new conversion result and
overwrite error is generated. Therefore, it is necessary to reset the ADCF by reading the conversion data
before completing the next A/D conversion.
D[7:6]
Reserved
D5
ADOIE: Overwrite Interrupt Enable Bit
Permits or prohibits the generation of overwrite interruption of A/D conversion result for CPU.
1 (R/W) : Interruption permitted
0 (R/W) : Interruption prohibited
In the interruption enable bit that controls the overwrite interruption of A/D conversion result, when
ADOIE is set to 1, interruption is permitted and when it sets to 0, interruption is prohibited. ADOIE is
set to 0 (Interruption prohibition) at the time of initial reset.
D4
ADCIE: Conversion-complete Interrupt Enable Bit
Permits or prohibits the generation of A/D conversion complete interrupt for CPU.
1 (R/W) : Interruption permitted
0 (R/W) : Interruption prohibited
In the interruption enable bit that controls the A/D conversion complete interruption, when ADCIE is
set to 1, interruption is permitted and when it sets to 0, interruption is prohibited. ADCIE is set to 0
(Interruption prohibition) at the time of initial reset.
D[3:2]
Reserved
D1
ADCTL: Conversion Control Bit
Controls the A/D conversion.
1 (R/W) : Software trigger
0 (R/W) : A/D conversion stop
If the A/D conversion is started by software trigger, 1 is written to ADCTL. In case of other trigger
methods, ADCTL is set to 1 by hardware.
ADCTL retained to 1 during A/D conversion.
At the time of single conversion mode, if the A/D conversion of specified channels is stopped, ADCTL
returns to 0 and A/D conversion circuit is stopped. When A/D conversion of continuous mode is
stopped, write 0 to ADCTL.
When ADEN is 0 (A/D conversion prohibited status) ADCTL is fixed to 0 and trigger is not received.
ADCTL is set to 0 (A/D conversion stop) at the time of initial reset.
D0
ADEN: A/D Enable Bit
Set the A/D converter to enable (conversion possible status).
1 (R/W) : Enable
0 (R/W) : Disable
A/D converter is enabled by writing 1 to ADEN and it is a condition where A/D conversion (trigger can
be received) can be started. When ADEN is 0, A/D converter is set to default status and trigger is not
received.
Furthermore, when the A/D converter of mode and start/complete channels is to be set, it is set after
setting ADEN to 0 in order to avoid the error operation.
ADEN is set to 0 (disable) at the time of initial reset.