Appendix A: I/O Register List
AP-12
EPSON
S1C17602 TECHNICAL MANUAL
0x4306–0x4318
Interrupt Controller
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Interrupt Level
Setup Register 0
(ITC_LV0)
0x4306
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV1[2:0]
P1 interrupt level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV0[2:0]
P0 interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 1
(ITC_LV1)
0x4308
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV3[2:0]
CT interrupt level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV2[2:0]
SWT interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 2
(ITC_LV2)
0x430a
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV5[2:0]
SVD interrupt level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV4[2:0]
T8OSC1 interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 3
(ITC_LV3)
0x430c
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV7[2:0]
T16E Ch.0 interrupt level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV6[2:0]
LCD interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 4
(ITC_LV4)
0x430e
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV9[2:0]
T16 Ch.0 interrupt level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV8[2:0]
T8F Ch.0/Ch.1 interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 5
(ITC_LV5)
0x4310
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV11[2:0]
T16 Ch.2 interrupt level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV10[2:0]
T16 Ch.1 interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 6
(ITC_LV6)
0x4312
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV13[2:0]
UART Ch.1/I2C slave interrupt
level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV12[2:0]
UART Ch.0 interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 7
(ITC_LV7)
0x4314
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV15[2:0]
I2C Master interrupt level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV14[2:0]
SPI interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 8
(ITC_LV8)
0x4316
(16 bits)
D15–3 –
reserved
–
0 when being read.
D2–0 ILV16[2:0]
REMC interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 9
(ITC_LV9)
0x4318
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV19[2:0]
RFC interrupt level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV18[2:0]
ADC10SA interrupt level
0 to 7
0x0 R/W