21 I2C Slave (I2CS)
21-20
EPSON
S1C17602 TECHNICAL MANUAL
0x4368: I2C Slave Status Register (I2CS_STAT)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
I2C Slave
Status Register
(I2CS_STAT)
0x4368
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7
BSTAT
Bus status transition
1 Changed
0 Unchanged
0
R
D6
–
reserved
–
0 when being read.
D5
TXUDF
Transmit data underflow
1 Occurred
0 Not occurred
0
R/W Reset by writing 1.
RXOVF
Receive data overflow
D4
BFREQ
Bus free request
1 Occurred
0 Not occurred
0
R/W
D3
DMS
Output data mismatch
1 Error
0 Normal
0
R/W
D2
ASDET
Async. address detection status
1 Detected
0 Not detected
0
R/W
D1
DA_NAK
NAK receive status
1 NAK
0 ACK
0
R/W
D0
DA_STOP
STOP condition detect
1 Detected
0 Not detected
0
R/W
D[15:8]
Reserved
D7
BSTAT: Bus Status Transition Bit
Indicates transition of the bus status.
1 (R):
Changed
0 (R):
Unchanged (default)
When one of the TXUDF/RXOVF (D5), BFREQ (D4), DMS (D3), ASDET (D2), DA_NAK (D1), and
DA_STOP (D0) bits is set to 1, BSTAT is also set to 1 and an interrupt signal is output to the ITC if the
interrupt is enabled with BSTAT_IEN (D2/I2CS_ICTL register). This interrupt can be used to perform
an error or terminate handling. BSTAT will be reset to 0 when the TXUDF/RXOVF (D5), BFREQ (D4),
DMS (D3), ASDET (D2), DA_NAK (D1), and DA_STOP (D0) bits are all reset to 0.
D6
Reserved
D5
TXUDF: Transmit Data Underflow Bit (for transmission)
RXOVF: Receive Data Overflow Bit (for reception)
Indicates the transmit/receive data register status.
1 (R/W): Data underflow/overflow has been occurred
0 (R/W): Data underflow/overflow has not been occurred (default)
This bit is effective during transmission/reception when the clock stretch function is disabled. If a
data transmission begins before transmit data is written to the I2CS_TRNS register, it is regarded as
a transmit data underflow and TXUDF is set to 1. If the next data reception has completed before the
received data is read from the I2CS_RECV register and the I2CS_RECV register value is overwritten
with the newly received data, it is regarded as a data overflow and RXOVF is set to 1.
At the same time, an interrupt signal is output to the ITC if the interrupt is enabled with BSTAT_IEN
(D2/I2CS_ICTL register). This interrupt can be used to perform an error handling.
After TXUDF/RXOVF is set to 1, it is reset to 0 by writing 1.
D4
BFREQ: Bus Free Request Bit
Indicate the I2C bus free request input status.
1 (R/W): Request has been issued
0 (R/W): Request has not been issued (default)
If BFREQ_EN (D4/I2CS_CTL register) has been set to 1 (bus free request enabled), a low pulse longer
than five system clock (PCLK) cycles input to the #BFR pin sets BFREQ to 1 and the bus free request is
accepted. When a bus free request is accepted, the I2C slave module initializes the I2C communication
process and puts the SDA1 and SCL1 pins into high-impedance state. The control registers will not be
initialized in this process.
At the same time, an interrupt signal is output to the ITC if the interrupt is enabled with BSTAT_IEN
(D2/I2CS_ICTL register). This interrupt can be used to perform an error handling.
After BFREQ is set to 1, it is reset to 0 by writing 1.
If BFREQ_EN is set to 0, low pulse inputs to the #BFR pin are ignored and BFREQ is not set to 1.