Appendix A: I/O Register List
AP-26
EPSON
S1C17602 TECHNICAL MANUAL
0x5214–0x523a
P Port & Port MUX
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
P1 Port Schmitt
Trigger Control
Register
(P1_SM)
0x5214
(8 bits)
D7–0 P1SM[5:0] P1[5:0] port Schmitt trigger input
enable
1 Enable
(Schmitt)
0 Disable
(CMOS)
1
(0xff)
R/W
P1 Port
Interrupt Mask
Register
(P1_IMSK)
0x5215
(8 bits)
D7–0 P1IE[7:0]
P1[7:0] port interrupt enable
1 Enable
0 Disable
0
R/W
P1 Port
Interrupt Edge
Select Register
(P1_EDGE)
0x5216
(8 bits)
D7–0 P1EDGE[7:0] P1[7:0] port interrupt edge select
1 Falling edge 0 Rising edge
0
R/W
P1 Port
Interrupt Flag
Register
(P1_IFLG)
0x5217
(8 bits)
D7–0 P1IF[7:0]
P1[7:0] port interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
P1 Port
Chattering
Filter Control
Register
(P1_CHAT)
0x5218
(8 bits)
D7
–
reserved
–
0 when being read.
D6–4 P1CF2[2:0] P1[7:4] chattering filter time
P0CF2[2:0]
Filter time
0
R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
16384/fPCLK
8192/fPCLK
4096/fPCLK
2048/fPCLK
1024/fPCLK
512/fPCLK
256/fPCLK
None
0x0 R/W
D3
–
reserved
–
0 when being read.
D2–0 P1CF1[2:0] P1[3:0] chattering filter time
P0CF1[2:0]
Filter time
0x0 R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
16384/fPCLK
8192/fPCLK
4096/fPCLK
2048/fPCLK
1024/fPCLK
512/fPCLK
256/fPCLK
None
P1 Port Input
Enable Register
(P1_IEN)
0x521a
(8 bits)
D7–0 P1IEN[7:0] P1[7:0] port input enable
1 Enable
0 Disable
0xff R/W
P2 Port Input
Data Register
(P2_IN)
0x5220
(8 bits)
D7–0 P2IN[7:0]
P2[7:0] port input data
1 1 (H)
0 0 (L)
R
P2 Port Output
Data Register
(P2_OUT)
0x5221
(8 bits)
D7–0 P2OUT[7:0] P2[7:0] port output data
1 1 (H)
0 0 (L)
0
R/W
P2 Port
Output Enable
Register
(P2_OEN)
0x5222
(8 bits)
D7–0 P2OEN[7:0] P2[7:0] port output enable
1 Enable
0 Disable
0
R/W
P2 Port Pull-up
Control Register
(P2_PU)
0x5223
(8 bits)
D7–0 P2PU[7:0]
P2[7:0] port pull-up enable
1 Enable
0 Disable
1
(0xff)
R/W
P2 Port Input
Enable Register
(P2_IEN)
0x522a
(8 bits)
D7–0 P2IEN[7:0] P2[7:0] port input enable
1 Enable
0 Disable
0xff R/W
P3 Port Input
Data Register
(P3_IN)
0x5230
(8 bits)
D7–0 P3IN[7:0]
P3[7:0] port input data
1 1 (H)
0 0 (L)
R
P3 Port Output
Data Register
(P3_OUT)
0x5231
(8 bits)
D7–0 P3OUT[7:0] P3[7:0] port output data
1 1 (H)
0 0 (L)
0
R/W
P3 Port
Output Enable
Register
(P3_OEN)
0x5232
(8 bits)
D7–0 P3OEN[7:0] P3[7:0] port output enable
1 Enable
0 Disable
0
R/W
P3 Port Pull-up
Control Register
(P3_PU)
0x5233
(8 bits)
D7–0 P3PU[7:0]
P3[7:0] port pull-up enable
1 Enable
0 Disable
1
(0xff)
R/W
P3 Port Input
Enable Register
(P3_IEN)
0x523a
(8 bits)
D7–0 P3IEN[7:0] P3[7:0] port input enable
1 Enable
0 Disable
0xff R/W