18 UART
S1C17602 TECHNICAL MANUAL
EPSON
18-9
18.7 UART Interrupts
The UART includes a function for generating the following three different interrupt types.
Transmit buffer empty interrupt
Receive buffer full interrupt
Receive error interrupt
The UART outputs one interrupt signal shared by the three above interrupt factor types to the interrupt controller
(ITC). Inspect the status flag or error flag to determine the interrupt factor occurring.
Transmit buffer empty interrupt
To use this interrupt, set TIEN (D4/UART_CTLx register) to 1. If TIEN is set to 0 (default), interrupt requests
for this factor will not be sent to the ITC.
TIEN: Transmit Buffer Empty Interrupt Enable Bit in the UART Ch.x Control (UART_CTLx) Register
(D4/0x4104/0x4124)
When transmission data written to the transmit data buffer is transferred to the shift register, the UART sets the
TDBE bit (D0/UART_STx register) to 1, indicating that the transmit data buffer is empty. If transmit buffer
empty interrupts are permitted (TIEN = 1), an interrupt request pulse is sent simultaneously to the ITC.
TDBE: Transmit Data Buffer Empty Flag in the UART Ch.x Status (UART_STx) Register (D0/0x4100/0x4120)
An interrupt occurs if other interrupt conditions are met.
You can inspect the TDBE flag in the UART interrupt handler routine to determine whether the UART interrupt
is attributable to a transmit buffer empty. If TDBE is 0, the next transmission data can be written to the transmit
data buffer by the interrupt handler routine.
Receive buffer full interrupt
To use this interrupt, set RIEN (D5/UART_CTLx register) to 1. If RIEN is set to 0 (default), interrupt requests
for this factor will not be sent to the ITC.
RIEN: Receive Buffer Full Interrupt Enable Bit in the UART Ch.x Control (UART_CTLx) Register
(D5/0x4104/0x4124)
If the specified volume of received data is loaded into the receive data buffer when a receive buffer full interrupt
is permitted (RIEN = 1), the UART outputs an interrupt request pulse to the ITC. If RBFI (D1/UART_CTLx
register) is 0, an interrupt request pulse is output as soon as one item of received data is loaded into the receive
data buffer (RDRY flag (D1/UART_STx register) is set to 1). If RBFI (D1/UART_CTLx register) is 1, an
interrupt request pulse is output as soon as two items of received data are loaded into the receive data buffer
(RD2B flag (D3/UART_STx register) is set to 1).
RBFI: Receive Buffer Full Interrupt Condition Ch.x Setup Bit in the UART Control (UART_CTLx) Register
(D1/0x4104/0x4124)
RDRY: Receive Data Ready Flag in the UART Ch.x Status (UART_STx) Register (D1/0x4100/0x4120)
RD2B: Second Byte Receive Flag in the UART Ch.x Status (UART_STx) Register (D3/0x4100/0x4120)
An interrupt occurs if other interrupt conditions are met.
You can inspect the RDRY and RD2B flags in the UART interrupt handler routine to determine whether the
UART interrupt is attributable to a receive buffer full. If RDRY or RD2B is 1, the received data can be read
from the receive data buffer by the interrupt handler routine.
UART