Appendix A: I/O Register List
S1C17602 TECHNICAL MANUAL
EPSON
AP-3
AP
Peripheral circuit
Address
Register name
Function
P port & port MUX
(8-bit device)
0x5200
P0_IN
P0 Port Input Data Register
P0 port input data
0x5201
P0_OUT
P0 Port Output Data Register
P0 port output data
0x5202
P0_OEN
P0 Port Output Enable Register
P0 port output enable
0x5203
P0_PU
P0 Port Pull-up Control Register
P0 port pull-up control
0x5204
P0_SM
P0 Port Schmitt Trigger Control Register
P0 port Schmitt trigger control
0x5205
P0_IMSK
P0 Port Interrupt Mask Register
P0 port interrupt mask setting
0x5206
P0_EDGE
P0 Port Interrupt Edge Select Register
P0 port interrupt edge selection
0x5207
P0_IFLG
P0 Port Interrupt Flag Register
P0 port interrupt occurrence status display/reset
0x5208
P0_CHAT
P0 Port Chattering Filter Control Register
P0 port chattering filter control
0x5209
P0_KRST
P0 Port Key-Entry Reset Configuration Register P0 port key entry reset setting
0x520a
P0_IEN
P0 Port Input Enable Register
P0 port input enable
0x520b~0x520f –
–
Reserved
0x5210
P1_IN
P1 Port Input Data Register
P1 port input data
0x5211
P1_OUT
P1 Port Output Data Register
P1 port output data
0x5212
P1_OEN
P1 Port Output Enable Register
P1 port output enable
0x5213
P1_PU
P1 Port Pull-up Control Register
P1 port pull-up control
0x5214
P1_SM
P1 Port Schmitt Trigger Control Register
P1 port Schmitt trigger control
Only P15-10 can be controlled
0x5215
P1_IMSK
P1 Port Interrupt Mask Register
P1 port interrupt mask setting
0x5216
P1_EDGE
P1 Port Interrupt Edge Select Register
P1 port interrupt edge selection
0x5217
P1_IFLG
P1 Port Interrupt Flag Register
P1 port interrupt occurrence status display/reset
0x5218
P1_CHAT
P1 Port Chattering Filter Control Register
P1 port chattering filter control
0x5219~0x5219 –
–
Reserved
0x521a
P1_IEN
P1 Port Input Enable Register
P1 port input enable
0x521b~0x521f –
–
Reserved
0x5220
P2_IN
P2 Port Input Data Register
P2 port input data
0x5221
P2_OUT
P2 Port Output Data Register
P2 port output data
0x5222
P2_OEN
P2 Port Output Enable Register
P2 port output enable
0x5223
P2_PU
P2 Port Pull-up Control Register
P2 port pull-up control
0x5224~0x5229 –
–
Reserved
0x522a
P2_IEN
P2 Port Input Enable Register
P2 port input enable
0x522b~0x522f –
–
Reserved
0x5230
P3_IN
P3 Port Input Data Register
P3 port input data
0x5231
P3_OUT
P3 Port Output Data Register
P3 port output data
0x5232
P3_OEN
P3 Port Output Enable Register
P3 port output enable
0x5233
P3_PU
P3 Port Pull-up Control Register
P3 port pull-up control
0x5234~0x5239 –
–
Reserved
0x523a
P3_IEN
P3 Port Input Enable Register
P3 port input enable
0x523b~0x523f –
–
Reserved
0x5240
P4_IN
P4 Port Input Data Register
P4 port input data
0x5241
P4_OUT
P4 Port Output Data Register
P4 port output data
0x5242
P4_OEN
P4 Port Output Enable Register
P4 port output enable
0x5243
P4_PU
P4 Port Pull-up Control Register
P4 port pull-up control
0x5244~0x5249 –
–
Reserved
0x524a
P4_IEN
P4 Port Input Enable Register
P4 port input enable
0x524b~0x527f –
–
Reserved
0x52a0~0x52a1 P0_PMUX
P0 Port Function Select Register
P0 port function selection
0x52a2~0x52a3 P1_PMUX
P1 Port Function Select Register
P1 port function selection
0x52a4~0x52a5 P2_PMUX
P2 Port Function Select Register
P2 port function selection
0x52a6~0x52a7 P3_PMUX
P3 Port Function Select Register
P3 port function selection
0x52a8
P4_PMUX
P4 Port Function Select Register
P4 port function selection
0x52a9~0x52bf –
–
Reserved
PWM timer Ch.0
(16-bit device)
0x5300
T16E_CA
PWM Timer Compare Data A Register
Compare data A setting
0x5302
T16E_CB
PWM Timer Compare Data B Register
Compare data B setting
0x5304
T16E_TC
PWM Timer Counter Data Register
Counter data
0x5306
T16E_CTL
PWM Timer Control Register
Timer mode setting and timer RUN/STOP
0x5308
T16E_CLK
PWM Timer Input Clock Select Register
Prescaler output clock selection
0x530a
T16E_IMSK
PWM Timer Interrupt MASK Register
Interrupt factor mask selection
0x530c
T16E_IFLG
PWM Timer Interrupt Flag Register
Interrupt factor checking
0x530e~0x531f –
–
Reserved
MISC register
(16-bit device)
0x5320
MISC_FL
FLASHC/SRAMC Control Register
FLASHC/SRAMC access condition setting
0x5322
MISC_OSC1
OSC1 Peripheral Control Register
OSC1 operation peripheral function setting
for debugging
0x5324
MISC_PROT
MISC Protect Register
MISC register write protection
0x5326
MISC_IRAMSZ IRAM Size Select Register
IRAM size selection
0x5328
MISC_TTBRL
Vactor Table Address Low Register
Vector table address setting
0x532a
MISC_TTBRH Vector Table Address High Register
0x5323~0x533f –
–
Reserved