20 I2C Master (I2CM)
20-6
EPSON
S1C17602 TECHNICAL MANUAL
Transfer direction indicates the data transfer direction after the slave address. This is set to 0 when sending data
from the master to the slave and to 1 when receiving data from the slave.
To send a slave address, set the transmission address to RTDT[7:0] (D[7:0]/I2C_DAT register). At the same
time, set the TXE (D9/I2C_DAT register) transmitting the address to 1.
RTDT[7:0]: Receive/Transmit Data Bits in the I2C Data (I2C_DAT) Register (D[7:0]/0x4344)
TXE: Transmit Execution Bit in the I2C Data (I2C_DAT) Register (D9/0x4344)
After the slave address has been output, data can be sent and received as many times as required. Data must be
sent or received according to the transfer direction set together with the slave address.
Data transmission control
The procedure for transmitting data is described below. Data transmission is performed by the same procedure
as for slave address transmission.
To send byte data, set the transmission data to RTDT[7:0] (D[7:0]/I2C_DAT register). Set TXE (D9/I2C_DAT
register) to 1 to transmit 1 byte.
When TXE is set to 1, the I2C master module begins data transmission in sync with the clock. If the previous
data is currently being transmitted, data transmission starts after this has been completed.
The I2C master module first transfers the data written to the shift register, then starts outputting the clock from
SCL0. Resetting TXE to 0 at this point generates an interrupt, enabling the subsequent transmission data and
TXE to be reset.
The data bits in the shift register are shifted in sequence at the clock falling edge and output via the SDA0 pin
with the MSB leading.
The I2C master module outputs 9 clocks with each data transmission. In the 9th clock cycle, an ACK or NACK
is received from the slave device with the SDA0 signal as high impedance.
The slave device returns ACK(0) to the master if the data is received. If the data is not received, SDA is not
pulled down, which the I2C master module interprets to mean an NACK(1) (transmission failed).
SDA0 (output)
SDA0 (input)
SCL0 (output)
Start condition
1
2
8
9
D7
D6
D0
ACK
NACK
Figure 20.5.3: ACK and NACK
The I2C master module includes two status bits, TBUSY (D8/I2C_CTL register) and RTACK (D8/I2C_DAT
register), for transmission control.
TBUSY: Transmit Busy Flag in the I2C Control (I2C_CTL) Register (D8/0x4342)
RTACK: Receive/Transmit ACK Bit in the I2C Data (I2C_DAT) Register (D8/0x4344)
The TBUSY flag indicates the data transmission status. This flag becomes 1 when transmission starts (including
slave address transmission) and reverts to 0 once data transmission ends.
Inspect the flag to check whether the I2C master module is currently transmitting or at standby.
The RTACK bit indicates whether or not the slave device returned an ACK for the previous transmission.
RTACK is 0 if an ACK was returned and 1 if ACK was not returned.
Data receipt control
The procedure for receiving data is described below. To receive data, the slave address must be sent with the
transfer direction bit set to 1.
To receive data, set RXE (D10/I2C_DAT register) to 1 for receiving 1 byte.
TXE (D9/I2C_DAT register) is set to 1 when sending the slave address, but RXE can also be set to 1 at the
same time. If both TXE and RXE are set to 1, TXE takes priority.
RXE: Receive Execution Bit in the I2C Data (I2C_DAT) Register (D10/0x4344)