20 I2C Master (I2CM)
S1C17602 TECHNICAL MANUAL
EPSON
20-5
I2CM
20.5 Data Transfer Control
Make the following settings before starting data transfers.
(1) Set the 16-bit timer Ch.2 to output the I2C master clock. (See Section 11.)
(2) Select the option function. (See section 20.4.)
(3) Set the interrupt conditions to use I2C master interrupts. (See Section 20.6.)
Note: Make sure the I2C module is halted (when I2CEN/I2C_EN register = 0) before changing the
above settings.
I2CEN: I2C Enable Bit in the I2C Enable (I2C_EN) Register (D0/0x4340)
Permitting data transfers
Set the I2CEN (D0/I2C_EN register) to 1 to permit I2C operations. This enables I2C master transfers and
permits clock input/output.
Note: Do not set I2CEN to 0 when the I2C master module is transferring data.
Data transfer start
To start data transfers, the I2C master (this module) must generate the start condition. The slave address is then
sent to establish communications.
(1) Generate start condition
The start condition applies when the SCL line is maintained at High and the SDA line is maintained at Low.
SDA0 (output)
SCL0 (output)
Start condition
Figure 20.5.1: Start condition
The start condition is generated by setting STRT (D0/I2C_CTL register) to 1.
STRT: Start Control Bit in the I2C Control (I2C_CTL) Register (D0/0x4342)
STRT is automatically reset to 0 once the start condition is generated. The I2C bus is busy from this point on.
2 Slave address transmission
Once the start condition has been generated, the I2C master (this module) sends a bit indicating the slave
address and transfer direction for communications. I2C slave addresses are either 7-bit or 10-bit. This module
uses an 8-bit transfer data register to send the slave address and transfer direction bit, enabling single transfers
in 7-bit address mode. In 10-bit mode, data is sent twice under software control. Figure 20.5.2 gives the
configuration of the address data.
Slave address
7-bit address
Transfer direction
0: Master
→ Slave (data transmission)
1: Slave
→ Master (date receipt)
A6
A5
D7
D6
A4
D5
A3
D4
A2
D3
A1
D2
A0
D1
DIR
D0
Slave address last 8 bits
A7
A6
D7
D6
A5
D5
A4
D4
A3
D3
A2
D2
A1
D1
A0
D0
Slave address
first 2 bits
10-bit address
Transfer direction
0: Master
→ Slave (data transmission)
1: Slave
→ Master (date receipt)
1
First data sent
Second data sent
1
D7
D6
1
D5
1
D4
0
D3
A9
D2
A8
D1
DIR
D0
Figure 20.5.2: Slave address and transmission data specifying transfer direction