21 I2C Slave (I2CS)
S1C17602 TECHNICAL MANUAL
EPSON
21-17
I2CS
0x4366: I2C Slave Control Register (I2CS_CTL)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
I2C Slave
Control Register
(I2CS_CTL)
0x4366
(16 bits)
D15–9 –
reserved
–
0 when being read.
D8
TBUF_CLR I2CS_TRNS register clear
1 Clear state 0 Normal
0
R/W
D7
I2C_EN
I2C slave enable
1 Enable
0 Disable
0
R/W
D6
SOFTRESET Software reset
1 Reset
0 Cancel
0
R/W
D5
NAK_ANS NAK answer
1 NAK
0 ACK
0
R/W
D4
BFREQ_EN Bus free request enable
1 Enable
0 Disable
0
R/W
D3
CLKSTR_EN Clock stretch On/Off
1 On
0 Off
0
R/W
D2
NF_EN
Noise filter On/Off
1 On
0 Off
0
R/W
D1
ASDET_EN Async.address detection On/Off
1 On
0 Off
0
R/W
D0
COM_MODE I2C slave communication mode
1 Active
0 Standby
0
R/W NAK responsee
when standby
D[15:9]
Reserved
D8
TBUF_CLR: I2CS_TRNS Register Clear Bit
Clears the I2CS_TRNS register (0x4360).
1 (R/W): Clear state
0 (R/W): Normal state (clear state cancellation) (default)
When TBUF_CLR is set to 1, the I2CS_TRNS register enters clear state. After that writing 0 to
TBUF_CLR returns the I2CS_TRNS register to normal state. It is not necessary to insert a waiting time
between writing 1 and 0.
If a new transmission is started when the I2CS_TRNS register still stores data for the previous
transmission that has already finished, the data will be sent when TXEMP (D3/I2CS_ASTAT register)
is set. In order to avoid this problem, clear the I2CS_TRNS register using TBUF_CLR before starting
transmission (before slave selection). The clear operation is not required if transmit data is written to
the I2CS_TRNS register before TXEMP is set to 1.
Data can be written to the I2CS_TRNS register even if it is placed into clear state (TBUF_CLR = 1).
However, this writing does not reset TXEMP to 0. Note that TXEMP is not reset to 0 when TBUF_CLR
is set back to 0. Therefore, data must be written to the I2CS_TRNS register when TBUF_CLR = 0.
D7
I2C_EN: I2C Slave Enable Bit
Enables/disables operation of the I2C slave module.
1 (R/W): Enable
0 (R/W): Disable (default)
When I2C_EN is set to 1, the I2C slave module is activated and data transfer is enabled.
When I2C_EN is set to 0, the I2C slave module goes off.
D6
SOFTRESET: Software Reset Bit
Resets the I2C slave module.
1 (R/W): Reset
0 (R/W): Cancel reset state (default)
To reset the I2C slave module, write 1 to SOFTRESET to place the I2C slave module into reset status,
then write 0 to SOFTRESET to release it from reset status. It is not necessary to insert a waiting time
between writing 1 and 0. The I2C slave module initializes the I2C slave communication process and put
the SDA1 and SCL1 pins into high-impedance state to be ready to detect a start condition. Furthermore,
the I2C slave control bits except for SOFTRESET are initialized. Perform the software reset in the
initial setting process before staring communication.
D5
NAK_ANS: NAK Answer Bit
Specifies the acknowledge bit to be sent after data reception.
1 (R/W): NAK
0 (R/W): ACK (default)
When an eight-bit data is received, the I2C slave module sends back an ACK (SDA1 = low) or a NAK
(SDA1 = Hi-Z). Either ACK or NAK should be specified using NAK_ANS within 7 cycles of the I2C
slave clock (SCL1) after RXRDY has been set to 1 by receiving the previous data.