21 I2C Slave (I2CS)
21-4
EPSON
S1C17602 TECHNICAL MANUAL
21.4 Initializing the I2C Slave
21.4.1 Reset
The I2C slave module must be reset to initialize the communication process and to set the I2C bus into free status (high
impedance). The following shows two methods for resetting the module:
(1) Software reset
The I2C slave module can be reset by altering SOFTRESET (D6/I2CS_CTL register).
SOFTRESET: Software Reset Bit in the I2C Slave Control (I2CS_CTL) Register (D6/0x4366)
To reset the I2C slave module, write 1 to SOFTRESET to place the I2C slave module into reset status, then write
0 to SOFTRESET to release it from reset status. It is not necessary to insert a waiting time between writing 1
and 0.
The I2C slave module initializes the I2C slave communication process and put the SDA1 and SCL1 pins into
high-impedance state to be ready to detect a start condition. Furthermore, the I2C slave control bits except for
SOFTRESET are initialized.
Perform the software reset in the initial setting process before staring communication.
(2) Bus free request with an input from the #BFR pin
The I2C slave module can accept bus free requests using the #BFR pin input. The bus free request support is
disabled by default. To enable this function, set BFREQ_EN (D4/I2CS_CTL register) to 1.
BFREQ_EN: Bus Free Request Enable Bit in the I2C Slave Control (I2CS_CTL) Register (D4/0x4366)
When this function is enabled, a low pulse (five system clock (PCLK) cycles or more pulse width is required)
input to the #BFR pin sets BFREQ (D4/I2CS_STAT register) to 1. This initializes the I2C slave communication
process and puts the SDA1 and SCL1 pins into high-impedance state. The control registers will not be
initialized as distinct from the software reset described above.
BFREQ: Bus Free Request Bit in the I2C Slave Status (I2CS_STAT) Register (D4/0x4368)
Note: When BFREQ is set to 1 (an interrupt can be used for this check), perform the software reset and
set the registers again.
21.4.2 Setting the Slave Address
I2C slave devices have a unique slave address to identify each device.
The I2C slave module supports 7-bit address (does not support 10-bit address), and the address of this module must
be set to the I2CS_SADRS register (0x4364).
21.4.3 Optional Functions
The I2C slave module has a clock stretch, asynchronous address detection, and noise remove optional functions
selectable in the application program.
Clock stretch function
After data and ACK are transmitted or received, the slave device may issue a wait request to the master device
until it is ready to transmit/receive by pulling the SCL1 line down to low. The I2C slave module supports this
clock stretch function. The master device enters a standby state until the wait request is canceled (the SCL1
input goes high). The clock stretch function in this module is disabled by default. When using the clock stretch
function, set CLKSTR_EN (D3/I2CS_CTL register) to 1 before starting data communication.
CLKSTR_EN: Clock Stretch On/Off Bit in the I2C Slave Control (I2CS_CTL) Register (D3/0x4366)