24 A/D Converter (ADC10SA)
24-6
EPSON
S1C17602 TECHNICAL MANUAL
24.4 A/D Conversion Control and Operations
The following shows the process of A/D conversion operation
1. Activating A/D converter circuit
2. Starting A/D conversion
3. Reading A/D conversion result
4. Completing A/D conversion
Activating A/D converter circuit
After configuring settings shown in the previous section, write 1 to ADEN (DO/ADC10_CTL register)
to enable the A/D converter. This allows the A/D converter to permit a trigger to start A/D conversion. To
reconfigure or disable the A/D converter, set the ADEN bit to 0.
ADEN: A/D Enable Bit in the ADC10 Control/Status (ADC10_CTL) Register (D0/0x5384)
Starting A/D conversion
The A/D converter starts A/D conversion if a trigger is input when the ADEN bit is set to 1. When software
trigger is selected, A/D conversion starts by writing 1 to ADCTL (Dl/ADC10_CTL register).
ADCTL: A/D Conversion Control Bit in the ADC10 Control/Status (ADC10_CTL) Register (D1/0x5384)
Triggers other than selected by ADTS[1:0](D[5:4]/ADC10_TRG register) are not permitted.
ADTS[1:0]: A/D Conversion Trigger Selection Bits in the ADC10 Trigger/Channel Select (ADC10_TRG)
Register (D[5:4]/0x5382)
Once a trigger is input, the A/D converter processes the sampling of analog input signals from the conversion
starting channel selected by ADCS[2:0] (D[10:8]/ADC10_TRG register) to perform A/D conversion.
ADCS[2:0]: A/D Converter Start Channel Selection Bits in the ADC10 Trigger/Channel Select (ADC10_TRG)
Register (D[10:8]/0x5382)
The ADCTL bit used for software trigger turns to 1 even by the trigger of other type, enabling itself to be used
as the status bit for A/D conversion.
ADICH[2:0] (D[2=0]/ADC10_CTL register) can read the channel in conversion process.
ADICH[2:0]: Internal Conversion Channel Status Bits in the ADC10 Control/Status (ADC10_CTL) Register
(D[14:12]/0x5384)
Reading A/D conversion result
After completing A/D conversion, the A/D converter stores conversion result in 10-bit data register ADD[15:0]
(D[15:0]/ADC10_ADD register), and set the conversion complete flag ADCF (D8/ADC10_CTL register). If
ADCS[2:0] (D[10:8]/ADC10_TRG register) and ADCE[2:0] (D[13:11]/ADC10_TRG register) specify multiple
channels, the A/D converter continues A/D conversion for subsequent channels.
ADD[15:0]: A/D Converted Data Bits in the ADC10 Conversion Result (ADC10_ADD) Register
(D[15:0]/0x5380)
ADCF:
Conversion-Complete Flag Bit in the ADC10 Control/Status (ADC10_CTL) Register (D8/0x5384
ADCE[2:0]: End Channel Selection Bits in the ADC10 Trigger/Channel Select (ADC10_TRG) Register
(D[13:11]/0x5382)
A/D conversion result is stored in ADD[15:0] each time when conversion for a channel is completed. The
conversion complete interrupt can be generated concurrently with the storing. The interrupt is usually used to
read converted data. If you do not use the conversion complete interrupt, check that the conversion complete
factor ADCF (D8/ADD[15:0] register) is set to 1, and then read conversion result from ADD ADD[15:0]. By
reading the ADD [15:0] value, the conversion complete interrupt and the ADCF flag are automatically set to 0.