18 UART
18-6
EPSON
S1C17602 TECHNICAL MANUAL
S1: Start bit, S2: Stop bit, P: Parity bit,
Wr: data writing to transmit data buffer
Sampling clock
SOUT
TDBE
TRBS
Interrupt
S1 D0 D1 D2 D3 D4 D5 D6 D7 P S2 S1 D0 D1
D7 P S2 S1 D0 D1
D7 P
Wr
S2
Figure 18.5.1: Data transmission timing chart
Data reception control
The receiving circuit is launched by setting the RXEN bit to 1, enabling data to be received from an external
serial device.
When the external serial device sends the start bit, the receiving circuit detects its Low level and starts sampling
the following data bits. The data bits are sampled at the sampling clock rising edge, and the lead bit is loaded
into the receive shift register as LSB. Once the MSB has been received into the shift register, the received data
is loaded into the receive data buffer. If parity checking is enabled, the receiving circuit checks parity at the
same time by checking the parity bit received immediately after the MSB.
The receive data buffer, a 2-byte FIFO, receives data until full.
Received data in the buffer can be read from the UART_RXDx register (0x4102/0x4122). The oldest data is
read out first, clearing the register.
UART_RXDx: UART Ch.x Receive Data Register (0x4102/0x4122)
The receiving circuit includes the RDRY (D1/UART_STx register) and RD2B (D3/UART_STx register) buffer
status flags.
RDRY: Receive Data Ready Flag in the UART Ch.x Status (UART_STx) Register (D1/0x4100/0x4120)
RD2B: Second Byte Receive Flag in the UART Ch.x Status (UART_STx) Register (D3/0x4100/0x4120)
The RDRY flag indicates that the receive data buffer still contains data. The RD2B flag indicates that the
receive data buffer is full.
(1) RDRY = 0, RD2B = 0
The receive data buffer contents need not be read, since no data has been received.
(2) RDRY = 1, RD2B = 0
One data item has been received. Read the receive data buffer contents once to clear the data inside the
buffer and reset the RDRY flag. The buffer reverts to state (1) above.
If the receive data buffer contents are read twice, the second data read will be invalid.
(3) RDRY = 1, RD2B = 1
Two data items have been received. Read the receive data buffer contents twice. The receive data buffer
outputs the oldest data first, clearing the buffer data read out and resetting the RD2B flag. The buffer then
reverts to the state in (2) above. The second read outputs the most recent received data, after which the
buffer reverts to the state in (1) above.
Even when the receive buffer is full, the shift register can receive one more item of data. An overrun
error will occur if additional data is sent from the external serial device in this state, and the new data will
overprogram the shift register data. The contents of the receive data buffer must be read out before an
overrun error occurs. For detailed information on overrun errors, refer to Section 18.6.
The volume of data received can be checked by reading these flags.