![](http://datasheet.mmic.net.cn/140000/S1C17602F00E100_datasheet_5011484/S1C17602F00E100_480.png)
27 On-chip Debugger (DBG)
27-8
EPSON
S1C17602 TECHNICAL MANUAL
0xffffa0: Debug Control Register (DCR)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Debug Control
Register
(DCR)
0xffffa0
(8 bits)
D7
IBE4
Instruction break #4 enable
1 Enable
0 Disable
0
R/W
D6
IBE3
Instruction break #3 enable
1 Enable
0 Disable
0
R/W
D5
IBE2
Instruction break #2 enable
1 Enable
0 Disable
0
R/W
D4
DR
Debug request flag
1 Occurred
0 Not occurred
0
R/W Reset by writing 1.
D3
IBE1
Instruction break #1 enable
1 Enable
0 Disable
0
R/W
D2
IBE0
Instruction break #0 enable
1 Enable
0 Disable
0
R/W
D1
SE
Single step enable
1 Enable
0 Disable
0
R/W
D0
DM
Debug mode
1 Debug mode 0 User mode
0
R
D7
IBE4: Instruction Break #4 Enable Bit
Permits or prohibits instruction break #4.
1(R/W): Permit
0(R/W): Prohibit (default)
If this bit is set to 1, the instruction fetch address and the value set in the Instruction Break Address
Register 4 (0xffffd0) are compared. If they match, an instruction break is generated. If this bit is set to 0,
no comparison is performed.
D6
IBE3: Instruction Break #3 Enable Bit
Permits or prohibits instruction break #3.
1(R/W): Permit
0(R/W): Prohibit (default)
If this bit is set to 1, the instruction fetch address and the value set in the Instruction Break Address
Register 3 (0xffffbc) are compared. If they match, an instruction break is generated. If this bit is set to 0,
no comparison is performed.
D5
IBE2: Instruction Break #2 Enable Bit
Permits or prohibits instruction break #2.
1(R/W): Permit
0(R/W): Prohibit (default)
If this bit is set to 1, the instruction fetch address and the value set in the Instruction Break Address
Register 2 (0xffffb8) are compared. If they match, an instruction break is generated. If this bit is set to 0,
no comparison is performed.
D4
DR: Debug Request Flag
Indicates the presence or absence of an external debug request.
1(R): Request generated
0(R): None (default)
1(W): Resets flag
0(W): Invalid
This flag is cleared (reset to 0) when 1 is written. It must be cleared before the debug processing routine
is terminated by the retd instruction.
D3
IBE1: Instruction Break #1 Enable Bit
Permits or prohibits instruction break #1.
1(R/W): Permit
0(R/W): Prohibit (default)
If this bit is set to 1, the instruction fetch address and the value set in the Instruction Break Address
Register 1 (0xffffb4) are compared. If they match, an instruction break is generated. If this bit is set to 0,
no comparison is performed.