21 I2C Slave (I2CS)
S1C17602 TECHNICAL MANUAL
EPSON
21-21
I2CS
D3
DMS: Output Data Mismatch Bit
Represents the results of comparison between output data and SDA1 line status.
1 (R/W): Error has been occurred
0 (R/W): Error has not been occurred (default)
The SDA1 line status during data transmission is input in the module and is compare with the output
data. The comparison results are set to DMS. DMS is set to 0 when data is output correctly. If the
SDA1 line status is different from the output data, DMS is set to 1. This may be caused by a low pull-
up resistor value or another device that is controlling the SDA1 line. At the same time, an interrupt
signal is output to the ITC if the interrupt is enabled with BSTAT_IEN (D2/I2CS_ICTL register). This
interrupt can be used to perform an error handling.
After DMS is set to 1, it is reset to 0 by writing 1.
Note: When the master device of the I2C bus, which has multiple slave devices connected including
this IC, starts communication with another slave device, the I2C slave module of this IC issues
NAK in response to the sent slave address. On the other hand, the selected slave device
issues ACK. Therefore, DMS may be set due to a difference between the output value of this
IC and the SDA1 line status. When SELECTED (D1/I2CS_ASTAT register) is set to 0, you can
ignore DMS without a problem even if it is set to 1 as there is a difference in the response
code (ACK/NAK) from the selected slave device.
When the I2C slave is placed into asynchronous address detection mode, a DMS does not
occur as in the condition above.
D2
ASDET: Async. Address Detection Status Bit
Indicates the asynchronous address detection status.
1 (R/W): Detected
0 (R/W): Not detected (default)
The I2C slave module operation clock (PCLK) frequency must be set eight-times or higher than the
transfer rate during data transfer. However, the PCLK frequency can be lowered to reduce current
consumption if no other processing is required during standby for data transfer. The asynchronous
address detection function is provided to detect the I2C slave address sent from the master in this status.
ASDET is set to 1 if the slave address of the I2C slave module is detected when the asynchronous
address detection function has been enabled by setting ASDET_EN (D1/I2CS_CTL register). The
I2C slave module returns a NAK to the I2C master to request for resending the slave address. At the
same time, an interrupt signal is output to the ITC if the interrupt is enabled with BSTAT_IEN (D2/
I2CS_ICTL register). Set the PCLK frequency to eight-times or higher than the transfer rate and reset
ASDET_EN to 0 in the interrupt handler routine. Data transfer will be able to resume normally after the
master retries transmission.
After ASDET is set to 1, it is reset to 0 by writing 1.
D1
DA_NAK: NAK Receive Status Bit
Indicates the acknowledge bit returned from the master.
1 (R/W): NAK
0 (R/W): ACK (default)
DA_NAK is set to 0 when an ACK is returned from the master after an eight-bit data has been sent.
This indicates that the master could receive data. If DA_NAK is 1, it indicates that the master could not
receive data or the master terminates data reception. At the same time DA_NAK is set to 1, an interrupt
signal is output to the ITC if the interrupt is enabled with BSTAT_IEN (D2/I2CS_ICTL register). This
interrupt can be used to perform an error handling.
After DA_NAK is set to 1, it is reset to 0 by writing 1.