21 I2C Slave (I2CS)
S1C17602 TECHNICAL MANUAL
EPSON
21-11
I2CS
21.6 I2C Slave Interrupt
The I2C slave module can generate the following three types of interrupts:
Transmit interrupt
Receive interrupt
Bus status interrupt
Transmit interrupt
When the transmit data written to SDATA[7:0] (D[7:0]/I2CS_TRNS register) is sent to the shift register,
TXEMP (D3/I2CS_ASTAT register) is set to 1 and an interrupt signal is output to the ITC. This interrupt can be
used to write the next transmit data to SDATA[7:0].
SDATA[7:0]: I2C Slave Transmit Data Bits in the I2C Slave Transmit Data (I2CS_TRNS) Register (D[7:0]/0x4360)
TXEMP: Transmit Data Empty Bit in the I2C Slave Access Status (I2CS_ASTAT) Register (D3/0x436a)
Set TXEMP_IEN (D0/I2CS_ICTL register) to 1 when using this interrupt. If TXEMP_IEN is set to 0 (default),
an interrupt request by this cause will not be sent to the ITC.
TXEMP_IEN: Transmit Interrupt Enable Bit in the I2C Slave Interrupt Control (I2CS_ICTL) Register (D0/0x436c)
Receive interrupt
When the received data is loaded to RDATA[7:0] (D[7:0]/I2CS_RECV register), RXRDY (D4/I2CS_ASTAT
register) is set to 1 and an interrupt signal is output to the ITC. This interrupt can be used to read the received
data from RDATA[7:0].
RDATA[7:0]: I2C Slave Receive Data Bits in the I2C Slave Receive Data (I2CS_RECV) Register (D[7:0]/0x4362)
RXRDY: Receive Data Ready Bit in the I2C Slave Access Status (I2CS_ASTAT) Register (D4/0x436a)
Set RXRDY_IEN (D1/I2CS_ICTL register) to 1 when using this interrupt. If RXRDY_IEN is set to 0 (default),
an interrupt request by this cause will not be sent to the ITC.
RXRDY_IEN: Receive Interrupt Enable Bit in the I2C Slave Interrupt Control (I2CS_ICTL) Register (D1/0x436c)
Bus status interrupt
The I2C slave module provides the status bits listed below to represent the transmit/receive and I2C bus statuses
(see Section 21.5 for details of each function).
1. ASDET: set to 1 when the slave address is detected by the asynchronous address detection function
ASDET: Async. Address Detection Status Bit in the I2C Slave Status (I2CS_STAT) Register (D2/0x4368)
2. TXUDF: set to 1 when a transmit operation has started before transmit data is written
(when the clock stretch function is disabled)
TXUDF: Transmit Data Underflow Bit in the I2C Slave Status (I2CS_STAT) Register (D5/0x4368)
3. DA_NAK: set to 1 when a NAK is returned from the master during transmission
DA_NAK: NAK Receive Status Bit in the I2C Slave Status (I2CS_STAT) Register (D1/0x4368)
4. DMS: set to 1 when the SDA1 line status is different from transfer data
DMS: Output Data Mismatch Bit in the I2C Slave Status (I2CS_STAT) Register (D3/0x4368)
DMA will also be set to 1 when another slave device issues ACK to this I2C slave address (when
ASDET_EN (D1/I2CS_CTL register) = 0).
Note: When the master device of the I2C bus, which has multiple slave devices connected
including this IC, starts communication with another slave device, the I2C slave module of
this IC issues NAK in response to the sent slave address. On the other hand, the selected
slave device issues ACK. Therefore, DMS may be set due to a difference between the
output value of this IC and the SDA1 line status. When SELECTED (D1/I2CS_ASTAT
register) is set to 0, you can ignore DMS without a problem even if it is set to 1 as there is
a difference in the response code (ACK/NAK) from the selected slave device.
When the I2C slave is placed into asynchronous address detection mode, a DMS does not
occur as in the condition above.