6 Interrupt Controller
6-4
EPSON
S1C17602 TECHNICAL MANUAL
If interrupt requests are input to the ITC simultaneously from multiple peripheral modules, the ITC outputs the
interrupt request with the highest priority to the S1C17 core in accordance with the following conditions.
1. Interrupts with the highest interrupt level take precedence.
2. If multiple interrupt requests are input with the same interrupt level, the interrupt with the lowest vector number
takes precedence.
The other interrupts occurring at the same time are held until all have been accepted by the S1C17 core, in
descending order of priority.
If an interrupt cause with higher priority occurs while the ITC is outputting an interrupt request signal to the S1C17
core (before being accepted by the S1C17 core), the ITC alters the vector number and interrupt level signal to the
setting information on the more recent interrupt. The previously occurring interrupt is held.
No interrupt is generated if the interrupt flag is reset via software within the peripheral module outputting an
interrupt request held.
6.3.3 S1C17 Core Interrupt Processing
Maskable interrupts for the S1C17 core occur when all of the following conditions are met:
Interrupts are permitted by the interrupt control bit inside the peripheral module.
The PSR (S1C17 core internal processor status register) IE (interrupt enable) bit has been set to 1.
The interrupt factor has a higher interrupt level set than that set for the PSR IL (interrupt level).
No other interrupt factors having higher procedence (e.g., NMI) are present.
If an interrupt cause permitted inside the peripheral module occurs, the corresponding interrupt flag is set to 1, and
this state is maintained until it is reset by the program. This means the interrupt cause is not cleared even if the
conditions listed above are not met when the interrupt cause occurs. An interrupt occurs if the above conditions are
met.
If multiple maskable interrupt causes arise simultaneously, the interrupt cause with the highest interrupt level and
lowest vector number becomes the subject of the interrupt request to the S1C17 core. Interrupts with lower levels
are held until the above conditions are subsequently met.
The S1C17 core samples interrupt requests for each cycle. On accepting an interrupt request, the S1C17 core
switches to interrupt processing when execution of the current instruction is complete.
Interrupt processing involves the following steps:
(1) The PSR and current program counter (PC) value is moved to the stack.
(2) The PSR IE bit is reset to 0 (preventing subsequent maskable interrupts).
(3) The PSR IL is set to the received interrupt level. (The NMI does not affect interrupt levels.)
(4) The vector for the interrupt factor occurring is loaded to the PC to execute the interrupt processing routine.
When an interrupt is received, (2) prevents subsequent maskable interrupts. Setting the IE bit to 1 within the
interrupt processing routine allows handling of multiple interrupts. In this case, IL is changed by (3), and only
interrupts with higher levels than those already being processed will be accepted.
Ending interrupt processing routines using a reti instruction returns the PSR to the state before the interrupt. The
program resumes processing following the instruction being executed at the time the interrupt occurred via the next
branch.