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21 I2C Slave (I2CS)
S1C17602 TECHNICAL MANUAL
EPSON
21-7
I2CS
Data transmission
The following describes a data transmission procedure.
The I2C slave module starts data transmit process when both SELECTED and R/W are set to 1. It sets TXEMP
(D3/I2CS_ASTAT register) to 1 to issue a request to the application program to write transmit data. Write
transmit data to SDATA[7:0] (D[7:0]/I2CS_TRNS register).
TXEMP: Transmit Data Empty Bit in the I2C Slave Access Status (I2CS_ASTAT) Register (D3/0x436a)
SDATA[7:0]: I2C Slave Transmit Data Bits in the I2C Slave Transmit Data (I2CS_TRNS) Register (D[7:0]/0x4360)
When setting the first transmit data after this module has been selected as the slave device, follow the
precautions described below.
When the clock stretch function is disabled (default)
Transmit data must be written to SDATA[7:0] within 1 cycle of the I2C slave clock (SCL1) after TXEMP
has been set to 1. This time is not enough for data preparation, so write transmit data before TXEMP has
been set to 1. If the previous transmit data is still stored in SDATA[7:0], it is overwritten with the new data
to be transferred. Therefore, the clear operation (see below) using TBUF_CLR is unnecessary.
When the clock stretch function is enabled
The master device is placed into wait status by the clock stretch function, so transmit data can be written
after TXEMP is set. However, if the previous transmit data is still stored in SDATA[7:0], it will be sent
immediately after TXEMP has been set. In order to avoid this problem, clear the I2CS_TRNS register using
TBUF_CLR (D8/I2CS_CTL register) before this module is selected as the slave device. The I2CS_TRNS
register is cleared by writing 1 to TBUF_CLR then writing 0 to it.
TBUF_CLR: I2CS_TRNS Register Clear Bit in the I2C Slave Control (I2CS_CTL) Register (D8/0x4366)
It is not necessary to clear the I2CS_TRNS register if the first transmit data is written before TXEMP has
been set.
For writing transmit data other than the first time, use an interrupt that can be generated when TXEMP is set
to 1.TXEMP is also set to 1 when the transmit data written to SDATA[7:0] is loaded to the sift register during
transmission. TXEMP is cleared by writing transmit data to SDATA[7:0].
When the clock stretch function is disabled (default)
When the clock stretch function has been disabled, data must be written to the I2CS_TRNS register within
7 cycles of the I2C slave clock (SCL1) from TXEMP being set to 1.
If data has not been written in this period, the current register value (previous transmit data) will be sent.
In this case, TXUDF (D5/I2CS_STAT register) is set to 1 to indicate that invalid data has been sent. An
interrupt can be generated when TXUDF is set to 1, so an error handling should be performed in the
interrupt handler routine. TXUDF is cleared by writing 1.
TXUDF: Transmit Data Underflow Bit in the I2C Slave Status (I2CS_STAT) Register (D5/0x4368)
When the clock stretch function is enabled
When the clock stretch function has been enabled, the I2C slave module pulls down the SCL1 pin to low to
generate a clock stretch (wait) status until transmit data is written to the I2CS_TRNS register.
Transmit data bits are output from the SDA1 pin in sync with the SCL1 input clock sent from the master. The
MSB is output first. After the eight bits has been output, the master sends back an ACK or NAK in the ninth
clock cycle.
SDA1 (output)
SDA1 (input)
SCL1 (input)
1
2
8
9
D7
D6
D0
ACK
NAK
Figure 21.5.2 ACK and NAK